You can get current thermal by
> cat /sys/class/thermal/thermal_zone?/temp
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add SCIF serial port support to the r8a7778 SoC by
adding platform devices together with clock bindings.
DT device description is excluded at this point since
such bindings are still under development.
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add initial support for the R8A7778 R-Car M1A SoC.
No static virtual mappings are used, all the components
make use of ioremap().
DT_MACHINE_START is still wrapped
in CONFIG_USE_OF to match other mach-shmobile code.

It is based on v1.0 datasheet
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

To reconfigure clocks, controlled by FRQCRA and FRQCRB, a kick bit has to
be set and to make sure the setting has taken effect, it has to be read
back repeatedly until it is cleared by the hardware. This patch adds the
waiting part, that was missing until now.
Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Magnus Damm <damm@opensource.se
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add a platform device for the r8a73a4 PFC.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add IRQC interrupt controller support to r8a73a4 by
hooking up two IRQC instances to handle 58 external
IRQ signals. There IRQC controllers are tied to SPIs
of the GIC. On r8a73a4 exact IRQ pin routing is handled
by the PFC which is excluded from this patch.

Both platform devices and DT devices are added in this
patch. The platform device versions are used to provide
a static interrupt map configuration for board code
written in C.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

V3 of SCIF serial port support for the r8a73a4 SoC.
This is done by adding platform devices for SCIFA0
-> SCIFA1 as well as SCIFB0 -> SCIFB3 together with
clock bindings. DT device description is excluded at
this point since such bindings are still under
development.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

V3 of initial support for the r8a73a4 SoC including:
 - Single Cortex-A15 CPU Core
 - GIC
 - Architecture timer

No static virtual mappings are used, all the components
make use of ioremap(). DT_MACHINE_START is still wrapped
in CONFIG_USE_OF to match other mach-shmobile code.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

The platform data for the INTC irq pin driver
seems to be global symbols, make it static to
allow multi-soc build.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

The platform data for the INTC irq pin driver
seems to be global symbols, make it static to
allow multi-soc build.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Update the r8a7779 IRQ code to make use of the
INTC External IRQ pin driver for external
interrupt pins IRQ0 -> IRQ3.

The r8a7779 SoC can like older SH SoCs configure
to use the IRQ0 -> IRQ3 signals as individual
interrupts or a combined IRL mode.

Without this patch the r8a7779 SoC code does
not fully support external IRQ pins in individual
IRQ mode. The r8a7779 PFC code does not yet have
gpio_to_irq() support so no need to update such
code.

At this point the DT reference implementations
are not covered. In the future such code shall
tie in the INTC External IRQ pin driver via
DT, so this kind of verbose code is not needed
for the long term DT case.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Tested-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Adjust the sh73a0 IRQ code to make use of the
INTC External IRQ pin driver for external
interrupt pins IRQ0 -> IRQ31.

This removes quite a bit of special-case code
in intc-sh73a0.c but the number of lines get
replaced with platform device information in
setup-sh73a0.c. The PFC code is also adjusted
to make gpio_to_irq() return the correct
interrupt number.

At this point the DT reference implementations
are not covered. In the future such code shall
tie in the INTC External IRQ pin driver via
DT, so this kind of verbose code is not needed
for the long term DT case.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add the macro irq_pin() to let board-specific code using
platform devices tie in external IRQn pins in a common way.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com>
[Rename device from to rcarfb to rcar-du]
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
[Manual conflict resolution]
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Commit "ARM: shmobile: r8a7779: use gic_iid macro" switched R8A7779 platform
devices to using gic_iid() macro instead of gic_spi() but commit "ARM: mach-
shmobile: r8a7779: add SATA support" added another use of gic_spi(). Convert
the SATA IRQ resource to using gic_iid().
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add SATA clock for r8a7779 SoC (for both device tree and usual cases).
Register SATA controller as a "late" platform device on r8a7779 SoC.
Signed-off-by: NVladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

move r8a7740_meram_workaround() to r8a7740 area
from r8a7779 area
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

"ARM: shmobile: add gic_iid macro for ICCIAR / interrupt ID"
enabled to use gic_iid macro.
This patch exchange current GIC interrupt setting
from gic_spi() to gic_iid()
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
[ horms+renesas@verge.net.au: Updated git commit id in changelog ]
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

r8a7779 is not sh73a0
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

R-Car H1 datasheet GIC number is indicating
GIC ICCIAR / interrupt ID number, not SPI number,
but current marzen board code is using gic_spi() with
un-understandable calculation.

This patch adds new gic_iid() macro which means
ICCIAR / interrupt ID, and used the number
currently written on datasheet.
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
[ horms+renesas@verge.net.au: Split board-marzen.c portion into a separate patch ]
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This adds temporarily the alternative device names to the clock list
that are used when booting via Device Tree setup.
Signed-off-by: NBastian Hecht <hechtb+renesas@gmail.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Each CPU Hotplug implementation for mach-shmobile
is now self-contained, so this change removes unused
helper code in hotplug.c. The two CPU Hotplug capable
SoCs sh73a0 and r8a7779 remain unchanged.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Update the r8a7779 SMP code and CPU Hotplug in particular
to follow the same style as sh73a0. This means dropping
__maybe_unused for #ifdef CONFIG_HOTPLUG_CPU.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Convert the sh73a0 CPU Hotplug code to use a local
implementation of ->cpu_disable(). With this change
in place the sh73a0 SMP code does no longer depend
on hotplug.c.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Update the SMP code for R8A7779 to make use of the
shared SCU function scu_power_mode() together with
the early setup code in shmobile_secondary_vector_scu.

With this patch in place the secondary CPUs modify the
SCU setting during early boot instead of letting other
CPUs deal with the coherency setting before boot. In
other words, we used to setup coherency before boot
in r8a7779_boot_secondary() but that bit is now instead
handled by the code in shmobile_secondary_vector_scu.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Update the r8a7779 CPU Hotplug code to use SCU PSR
to wait for the target CPU core. Previously the
shared code in hotplug.c was used to let cpu_kill()
wait for cpu_die(). With this change in place the
r8a7779 SMP code does not depend on hotplug.c anymore.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Rework the IOMEM() usage for the SCU base address in the
case of r8a7779. Adjusts the TWD to use R8A7779_SCU_BASE.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Rework the IOMEM() usage for the SCU base address in the
case of sh73a0. Removes recently introduced build warnings:

arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: initialization makes integer from pointer without a cast [enabled by default]
arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: (near initialization for 'twd_local_timer.res[0].start') [enabled by default]
arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: initialization makes integer from pointer without a cast [enabled by default]
/arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: (near initialization for 'twd_local_timer.res[0].end') [enabled by default]
Reported-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Rework the early SCU setup code in headsmp-scu.S to read
the base address in the same way as we use to fetch the
address of the invalidation function.
Reported-by: NBastian Hecht <hechtb@gmail.com>
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

It is sufficient to initialise i2c as a late device.

Cc: Magnus Damm <magnus.damm@gmail.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Do not initialise any early devices when using the minimal DT reference
code. Only the delay needs to be initialised.

Cc: Magnus Damm <magnus.damm@gmail.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Do not initialise any early devices when using the minimal DT reference
code. Only the delay needs to be initialised.

Cc: Magnus Damm <magnus.damm@gmail.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Remove warning about SMP not working with the
clock initialisation sheme used for reference DT.

This is resolved by not selecting CONFIG_PREEMPT.
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This a board to be brought up with SMP enabled
without a board file present.
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This is not needed as irq_set_wake is
only used for suspend to ram which is not
a requirement for bringing up boards using DT.
Reported-by: NMagnus Damm <magnus.damm@gmail.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Z and ZG clocks on sh73a0 have pll0 as their parent, not pll1.
Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Adjust emev2_init_delay() and emev2_add_standard_devices_dt()
to become static. They are not used outside this file anyway.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Update the SMP code for EMEV2 to make use of the
shared SCU function scu_power_mode() together with
the early setup code in shmobile_secondary_vector_scu.

With this patch in place the secondary CPUs modify the
SCU setting during early boot instead of letting other
CPUs deal with the coherency setting before boot. In
other words, we used to setup coherency before boot
in emev2_boot_secondary() but that bit is now instead
handled by the code in shmobile_secondary_vector_scu.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Update the code in headsmp-scu.S to use a global
shmobile_scu_base variable both for convenient SCU
base address storage and for the early SCU setup
code in shmobile_secondary_vector_scu.

With this patch applied r8a7779, sh73a0 and EMEV2
all make use of the global shmobile_scu_base
variable. However only sh73a0 makes use of the SCU
bring up code in shmobile_secondary_vector_scu.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Rename headsmp-sh73a0.S into headsmp-scu.S and
introduce shmobile_secondary_vector_scu().

The goal is to be able to share the function
above between all mach-shmobile SoCs that use
SCU for SMP. So far only sh73a0 use this.

At this time the SCU base address is still hard
coded in headsmp-scu.S to 0xf0000000, but this
will be changed in the future.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>