1. 03 6月, 2018 2 次提交
  2. 22 5月, 2018 1 次提交
  3. 11 5月, 2018 2 次提交
    • M
      powerpc/lib: Add alt patching test of branching past the last instruction · 6158faed
      Michael Ellerman 提交于
      Add a test of the relative branch patching logic in the alternate
      section feature fixup code. This tests that if we branch past the last
      instruction of the alternate section, the branch is not patched.
      That's because the assembler will have created a branch that already
      points to the first instruction after the patched section, which is
      correct and needs no further patching.
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      6158faed
    • M
      powerpc/lib: Fix the feature fixup tests to actually work · cad0e390
      Michael Ellerman 提交于
      The code patching code has always been a bit confused about whether
      it's best to use void *, unsigned int *, char *, etc. to point to
      instructions. In fact in the feature fixups tests we use both unsigned
      int[] and u8[] in different places.
      
      Unfortunately the tests that use unsigned int[] calculate the size of
      the code blocks using subtraction of those unsigned int pointers, and
      then pass the result to memcmp(). This means we're only comparing 1/4
      of the bytes we need to, because we need to multiply by
      sizeof(unsigned int) to get the number of *bytes*.
      
      The result is that the tests do all the patching and then only compare
      some of the resulting code, so patching bugs that only effect that
      last 3/4 of the code could slip through undetected. It turns out that
      hasn't been happening, although one test had a bad expected case (see
      previous commit).
      
      Fix it for now by multiplying the size by 4 in the affected functions.
      
      Fixes: 362e7701 ("powerpc: Add self-tests of the feature fixup code")
      Epic-brown-paper-bag-by: NMichael Ellerman <mpe@ellerman.id.au>
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      cad0e390
  4. 16 4月, 2018 1 次提交
    • M
      powerpc/lib: Fix off-by-one in alternate feature patching · b8858581
      Michael Ellerman 提交于
      When we patch an alternate feature section, we have to adjust any
      relative branches that branch out of the alternate section.
      
      But currently we have a bug if we have a branch that points to past
      the last instruction of the alternate section, eg:
      
        FTR_SECTION_ELSE
        1:     b       2f
               or      6,6,6
        2:
        ALT_FTR_SECTION_END(...)
               nop
      
      This will result in a relative branch at 1 with a target that equals
      the end of the alternate section.
      
      That branch does not need adjusting when it's moved to the non-else
      location. Currently we do adjust it, resulting in a branch that goes
      off into the link-time location of the else section, which is junk.
      
      The fix is to not patch branches that have a target == end of the
      alternate section.
      
      Fixes: d20fe50a ("KVM: PPC: Book3S HV: Branch inside feature section")
      Fixes: 9b1a735d ("powerpc: Add logic to patch alternative feature sections")
      Cc: stable@vger.kernel.org # v2.6.27+
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      b8858581
  5. 27 3月, 2018 1 次提交
  6. 21 1月, 2018 1 次提交
  7. 10 1月, 2018 1 次提交
    • M
      powerpc/64s: Add support for RFI flush of L1-D cache · aa8a5e00
      Michael Ellerman 提交于
      On some CPUs we can prevent the Meltdown vulnerability by flushing the
      L1-D cache on exit from kernel to user mode, and from hypervisor to
      guest.
      
      This is known to be the case on at least Power7, Power8 and Power9. At
      this time we do not know the status of the vulnerability on other CPUs
      such as the 970 (Apple G5), pasemi CPUs (AmigaOne X1000) or Freescale
      CPUs. As more information comes to light we can enable this, or other
      mechanisms on those CPUs.
      
      The vulnerability occurs when the load of an architecturally
      inaccessible memory region (eg. userspace load of kernel memory) is
      speculatively executed to the point where its result can influence the
      address of a subsequent speculatively executed load.
      
      In order for that to happen, the first load must hit in the L1,
      because before the load is sent to the L2 the permission check is
      performed. Therefore if no kernel addresses hit in the L1 the
      vulnerability can not occur. We can ensure that is the case by
      flushing the L1 whenever we return to userspace. Similarly for
      hypervisor vs guest.
      
      In order to flush the L1-D cache on exit, we add a section of nops at
      each (h)rfi location that returns to a lower privileged context, and
      patch that with some sequence. Newer firmwares are able to advertise
      to us that there is a special nop instruction that flushes the L1-D.
      If we do not see that advertised, we fall back to doing a displacement
      flush in software.
      
      For guest kernels we support migration between some CPU versions, and
      different CPUs may use different flush instructions. So that we are
      prepared to migrate to a machine with a different flush instruction
      activated, we may have to patch more than one flush instruction at
      boot if the hypervisor tells us to.
      
      In the end this patch is mostly the work of Nicholas Piggin and
      Michael Ellerman. However a cast of thousands contributed to analysis
      of the issue, earlier versions of the patch, back ports testing etc.
      Many thanks to all of them.
      Tested-by: NJon Masters <jcm@redhat.com>
      Signed-off-by: NNicholas Piggin <npiggin@gmail.com>
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      aa8a5e00
  8. 13 7月, 2017 1 次提交
  9. 02 3月, 2017 1 次提交
  10. 10 8月, 2016 1 次提交
  11. 03 8月, 2016 1 次提交
  12. 01 8月, 2016 4 次提交
  13. 21 7月, 2016 1 次提交
  14. 25 9月, 2014 1 次提交
  15. 16 11月, 2011 1 次提交
  16. 08 7月, 2010 1 次提交
    • S
      powerpc: Fix feature-fixup tests for gcc 4.5 · 3880ecb0
      Stephen Rothwell 提交于
      The feature-fixup test declare some extern void variables and then take
      their addresses.  Fix this by declaring them as extern u8 instead.
      
      Fixes these warnings (treated as errors):
      
        CC      arch/powerpc/lib/feature-fixups.o
      cc1: warnings being treated as errors
      arch/powerpc/lib/feature-fixups.c: In function 'test_cpu_macros':
      arch/powerpc/lib/feature-fixups.c:293:23: error: taking address of expression of type 'void'
      arch/powerpc/lib/feature-fixups.c:294:9: error: taking address of expression of type 'void'
      arch/powerpc/lib/feature-fixups.c:297:2: error: taking address of expression of type 'void'
      arch/powerpc/lib/feature-fixups.c:297:2: error: taking address of expression of type 'void'
      arch/powerpc/lib/feature-fixups.c: In function 'test_fw_macros':
      arch/powerpc/lib/feature-fixups.c:306:23: error: taking address of expression of type 'void'
      arch/powerpc/lib/feature-fixups.c:307:9: error: taking address of expression of type 'void'
      arch/powerpc/lib/feature-fixups.c:310:2: error: taking address of expression of type 'void'
      arch/powerpc/lib/feature-fixups.c:310:2: error: taking address of expression of type 'void'
      arch/powerpc/lib/feature-fixups.c: In function 'test_lwsync_macros':
      arch/powerpc/lib/feature-fixups.c:321:23: error: taking address of expression of type 'void'
      arch/powerpc/lib/feature-fixups.c:322:9: error: taking address of expression of type 'void'
      arch/powerpc/lib/feature-fixups.c:326:3: error: taking address of expression of type 'void'
      arch/powerpc/lib/feature-fixups.c:326:3: error: taking address of expression of type 'void'
      arch/powerpc/lib/feature-fixups.c:329:3: error: taking address of expression of type 'void'
      arch/powerpc/lib/feature-fixups.c:329:3: error: taking address of expression of type 'void'
      Signed-off-by: NStephen Rothwell <sfr@canb.auug.org.au>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      3880ecb0
  17. 26 2月, 2010 1 次提交
    • B
      powerpc: Fix lwsync feature fixup vs. modules on 64-bit · 3d98ffbf
      Benjamin Herrenschmidt 提交于
      Anton's commit enabling the use of the lwsync fixup mechanism on 64-bit
      breaks modules. The lwsync fixup section uses .long instead of the
      FTR_ENTRY_OFFSET macro used by other fixups sections, and thus will
      generate 32-bit relocations that our module loader cannot resolve.
      
      This changes it to use the same type as other feature sections.
      
      Note however that we might want to consider using 32-bit for all the
      feature fixup offsets and add support for R_PPC_REL32 to module_64.c
      instead as that would reduce the size of the kernel image. I'll leave
      that as an exercise for the reader for now...
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      3d98ffbf
  18. 17 2月, 2010 1 次提交
  19. 23 2月, 2009 1 次提交
    • K
      powerpc: Unify opcode definitions and support · 16c57b36
      Kumar Gala 提交于
      Create a new header that becomes a single location for defining PowerPC
      opcodes used by code that is either generationg instructions
      at runtime (fixups, debug, etc.), emulating instructions, or just
      compiling instructions old assemblers don't know about.
      
      We currently don't handle the floating point emulation or alignment decode
      as both are better handled by the specific decode support they already
      have.
      
      Added support for the new dcbzl, dcbal, msgsnd, tlbilx, & wait instructions
      since older assemblers don't know about them.
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      16c57b36
  20. 22 7月, 2008 1 次提交
  21. 03 7月, 2008 1 次提交
    • K
      powerpc: Fixup lwsync at runtime · 2d1b2027
      Kumar Gala 提交于
      To allow for a single kernel image on e500 v1/v2/mc we need to fixup lwsync
      at runtime.  On e500v1/v2 lwsync causes an illop so we need to patch up
      the code.  We default to 'sync' since that is always safe and if the cpu
      is capable we will replace 'sync' with 'lwsync'.
      
      We introduce CPU_FTR_LWSYNC as a way to determine at runtime if this is
      needed.  This flag could be moved elsewhere since we dont really use it
      for the normal CPU_FTR purpose.
      
      Finally we only store the relative offset in the fixup section to keep it
      as small as possible rather than using a full fixup_entry.
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      2d1b2027
  22. 01 7月, 2008 4 次提交
    • M
      powerpc: Add self-tests of the feature fixup code · 362e7701
      Michael Ellerman 提交于
      This commit adds tests of the feature fixup code, they are run during
      boot if CONFIG_FTR_FIXUP_SELFTEST=y. Some of the tests manually invoke
      the patching routines to check their behaviour, and others use the
      macros and so are patched during the normal patching done during boot.
      
      Because we have two sets of macros with different names, we use a macro
      to generate the test of the macros, very niiiice.
      Signed-off-by: NMichael Ellerman <michael@ellerman.id.au>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      362e7701
    • M
      powerpc: Add logic to patch alternative feature sections · 9b1a735d
      Michael Ellerman 提交于
      This commit adds the logic to patch alternative sections.  This is fairly
      straightforward, except for branches.  Relative branches that jump from
      inside the else section to outside of it need to be translated as they're
      moved, otherwise they will jump to the wrong location.
      Signed-off-by: NMichael Ellerman <michael@ellerman.id.au>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      9b1a735d
    • M
      powerpc: Introduce infrastructure for feature sections with alternatives · fac23fe4
      Michael Ellerman 提交于
      The current feature section logic only supports nop'ing out code, this means
      if you want to choose at runtime between instruction sequences, one or both
      cases will have to execute the nop'ed out contents of the other section, eg:
      
      BEGIN_FTR_SECTION
      	or	1,1,1
      END_FTR_SECTION_IFSET(FOO)
      BEGIN_FTR_SECTION
      	or	2,2,2
      END_FTR_SECTION_IFCLR(FOO)
      
      and the resulting code will be either,
      
      	or	1,1,1
      	nop
      
      or,
      	nop
      	or	2,2,2
      
      For small code segments this is fine, but for larger code blocks and in
      performance criticial code segments, it would be nice to avoid the nops.
      This commit starts to implement logic to allow the following:
      
      BEGIN_FTR_SECTION
      	or	1,1,1
      FTR_SECTION_ELSE
      	or	2,2,2
      ALT_FTR_SECTION_END_IFSET(FOO)
      
      and the resulting code will be:
      
      	or	1,1,1
      or,
      	or	2,2,2
      
      We achieve this by extending the existing FTR macros. The current feature
      section semantic just becomes a special case, ie. if the else case is empty
      we nop out the default case.
      
      The key limitation is that the size of the else case must be less than or
      equal to the size of the default case. If the else case is smaller the
      remainder of the section is nop'ed.
      
      We let the linker put the else case code in with the rest of the text,
      so that relative branches from the else case are more likley to link,
      this has the disadvantage that we can't free the unused else cases.
      
      This commit introduces the required macro and linker script changes, but
      does not enable the patching of the alternative sections.
      
      We also need to update two hand-made section entries in reg.h and timex.h
      Signed-off-by: NMichael Ellerman <michael@ellerman.id.au>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      fac23fe4
    • M
      powerpc: Split out do_feature_fixups() from cputable.c · 51c52e86
      Michael Ellerman 提交于
      The logic to patch CPU feature sections lives in cputable.c, but these days
      it's used for CPU features as well as firmware features.  Move it into
      it's own file for neatness and as preparation for some additions.
      
      While we're moving the code, we pull the loop body logic into a separate
      routine, and remove a comment which doesn't apply anymore.
      Signed-off-by: NMichael Ellerman <michael@ellerman.id.au>
      Acked-by: NKumar Gala <galak@kernel.crashing.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      51c52e86