This adds a driver for random number generator present on Broadcom
IPROC devices.
Reviewed-by: NRay Jui <rjui@broadcom.com>
Signed-off-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

Documents the IPROC random number generator device tree bindings
used in some Broadcom chipsets.
Reviewed-by: NRay Jui <rjui@broadcom.com>
Signed-off-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

Commit 7e933d3b ("crypto: ux500: use dmaengine_prep_slave_sg
API") changed the code to use the new API, but forgot to update an error
message.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

This is properly defined in the md5 header file.
Signed-off-by: NMartin Hicks <mort@bork.org>
Acked-by: NKim Phillips <kim.phillips@freescale.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

There were multiple loops in a row, for each separate step of the
initialization of the channels.  Simplify to a single loop.
Signed-off-by: NMartin Hicks <mort@bork.org>
Acked-by: NKim Phillips <kim.phillips@freescale.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

The DRBG code contains memset(0) calls to initialize a varaible
that are not necessary as the variable is always overwritten by
the processing.

This patch increases the CTR and Hash DRBGs by about 5%.
Signed-off-by: NStephan Mueller <smueller@chronox.de>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

The CTR DRBG only encrypts one single block at a time. Thus, use the
single block crypto API to avoid additional overhead from the block
chaining modes.

With the patch, the speed of the DRBG increases between 30% and 40%.

The DRBG still passes the CTR DRBG CAVS test.
Signed-off-by: NStephan Mueller <smueller@chronox.de>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

Integrate the module into the kernel config tree.
Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

Glue code for crypto infrastructure. Call the assembler
code where required. Take a little care about small input
data. Kick out early for input chunks < 64 bytes and replace
memset for context cleanup with simple loop.
Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

This is the assembler code for the MD5 implementation.
Handling of algorithm constants has been slightly
changed to reduce register usage and make better use
of cores with multiple ALUs. Thus they are stored as
delta values.
Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

Fix typo, "intialization" -> "initialization"
Signed-off-by: NColin Ian King <colin.king@canonical.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

Enable compilation of the AEAD AF_ALG support and provide a Kconfig
option to compile the AEAD AF_ALG support.
Signed-off-by: NStephan Mueller <smueller@chronox.de>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

This patch adds the AEAD support for AF_ALG.

The implementation is based on algif_skcipher, but contains heavy
modifications to streamline the interface for AEAD uses.

To use AEAD, the user space consumer has to use the salg_type named
"aead".

The AEAD implementation includes some overhead to calculate the size of
the ciphertext, because the AEAD implementation of the kernel crypto API
makes implied assumption on the location of the authentication tag. When
performing an encryption, the tag will be added to the created
ciphertext (note, the tag is placed adjacent to the ciphertext). For
decryption, the caller must hand in the ciphertext with the tag appended
to the ciphertext. Therefore, the selection of the used memory
needs to add/subtract the tag size from the source/destination buffers
depending on the encryption type. The code is provided with comments
explaining when and how that operation is performed.

A fully working example using all aspects of AEAD is provided at
http://www.chronox.de/libkcapi.htmlSigned-off-by: NStephan Mueller <smueller@chronox.de>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

The kernel crypto API has many indirections which warrant a description
as otherwise one can get easily lost. The description explains the
layers of the kernel crypto API based on examples.
Signed-off-by: NStephan Mueller <smueller@chronox.de>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

Integrate the module into the kernel config tree.
Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

Glue code for crypto infrastructure. Call the assembler
code where required. Disable preemption during calculation
and enable SPE instructions in the kernel prior to the
call. Avoid to disable preemption for too long.

Take a little care about small input data. Kick out early
for input chunks < 64 bytes and replace memset for context
cleanup with simple loop.
Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

This is the assembler code for SHA1 implementation with
the SIMD SPE instruction set. With the enhanced instruction
set we can operate on 2 32 bit words in parallel. That helps
reducing the time to calculate W16-W79. For increasing
performance even more the assembler function can compute
hashes for more than one 64 byte input block.

The state of the used SPE registers is preserved via the
stack so we can run from interrupt context. There might
be the case that we interrupt ourselves and push sensitive
data from another context onto our stack. Clear this area
in the stack afterwards to avoid information leakage.

The code is endian independant.
Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

Integrate the module into the kernel configuration
Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

Integrate the assembler modules into the kernel crypto
framework. Take care to avoid long intervals of disabled
preemption.
Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

The assembler block cipher module that controls the core
AES functions.
Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

Key generation for big endian core routines.
Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

The assembler AES encryption and decryption core routines.
Implemented & optimized for big endian. Nevertheless they
work on little endian too.

For most efficient reuse in (higher level) block cipher
routines they are implemented as "fast" call modules without
any stack handling or register saving. The caller must
take care of that part.
Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

4K AES tables for big endian. To reduce the possiblity of
timing attacks, the size has been cut to 8KB + 256 bytes
in contrast to 16KB in the generic implementation. That
is not perfect but at least a good tradeoff for CPU limited
router devices.
Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

Define some register aliases for better readability.
Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

Simplify the driver's probe function and error handling by using the
device managed allocators, while at it, drop the redundant "out of
memory" messages since these are already printed by the allocator.
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

Now that these definitions have been moved to
drivers/char/hw_random/bcm63xx-rng.c where they belong to make the
driver standalone, we can safely remove these definitions from
bcm63xx_regs.h.
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h contains the register
definitions for this random number generator block, incorporate these
register definitions directly into the bcm63xx-rng driver so we do not
rely on this header to be provided.
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

bcm_{readl,writel} macros expand to __raw_{readl,writel}, use these
directly such that we do not rely on the platform to provide these for
us. As a result, we no longer use bcm63xx_io.h, so remove that inclusion
too.
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

All possible code-paths will assign ret to suitable values so this
default value is not needed.
Signed-off-by: NNicholas Mc Guire <hofrat@osadl.org>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

A failure of sahara_hw_descriptor_create() with -EINVAL due to scatter list
out of bounds/invalid would not be reported back. This patch just passes on
the -EINVAL so it is visible in sahara_queue_manage().
Signed-off-by: NNicholas Mc Guire <hofrat@osadl.org>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

return type of wait_for_completion_timeout is unsigned long not int, this
patch adds appropriate variables of type unsigned long.
Signed-off-by: NNicholas Mc Guire <hofrat@osadl.org>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

return type of wait_for_completion_timeout is unsigned long not int, this
patch changes the type of ret from int to unsigned long.
Signed-off-by: NNicholas Mc Guire <hofrat@osadl.org>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

Changed the __driver-gcm-aes-aesni to be a proper aead algorithm.
This required a valid setkey and setauthsize functions to be added and also
some changes to make sure that math context is not corrupted when the alg is
used directly.
Note that the __driver-gcm-aes-aesni should not be used directly by modules
that can use it in interrupt context as we don't have a good fallback mechanism
in this case.
Signed-off-by: NAdrian Hoban <adrian.hoban@intel.com>
Signed-off-by: NTadeusz Struk <tadeusz.struk@intel.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

This patch enables VMX module in PPC64.
Signed-off-by: NLeonidas S. Barbosa <leosilva@linux.vnet.ibm.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

OpenSSL implements optimized ASM algorithms which support
VMX instructions on Power 8 CPU.

These scripts generate an endian-agnostic ASM implementation
in order to support both big and little-endian.
	- aesp8-ppc.pl: implements suport for AES instructions
	implemented by POWER8 processor.
	- ghashp8-ppc.pl: implements support for  GHASH for Power8.
	- ppc-xlate.pl:  ppc assembler distiller.

These code has been adopted from OpenSSL project in collaboration
with the original author (Andy Polyakov <appro@openssl.org>).
Signed-off-by: NLeonidas S. Barbosa <leosilva@linux.vnet.ibm.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

This patch adds GHASH routines to VMX module in order to
make use of VMX cryptographic acceleration instructions
on Power 8 CPU.
Signed-off-by: NLeonidas S. Barbosa <leosilva@linux.vnet.ibm.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

This patch adds AES CTR routines to VMX module in order to
make use of VMX cryptographic acceleration instructions
on Power 8 CPU.
Signed-off-by: NLeonidas S. Barbosa <leosilva@linux.vnet.ibm.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

This patch adds AES CBC routines to VMX module in order to
make use of VMX cryptographic acceleration instructions
on Power 8 CPU.
Signed-off-by: NLeonidas S. Barbosa <leosilva@linux.vnet.ibm.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

This patch adds AES routines to VMX module in order to
make use of VMX cryptographic acceleration instructions
on Power 8 CPU.
Signed-off-by: NLeonidas S. Barbosa <leosilva@linux.vnet.ibm.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

This patch adds routines supporting VMX instructions on the
Power 8.
Signed-off-by: NLeonidas S. Barbosa <leosilva@linux.vnet.ibm.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>