As it turns out more than just Armada 370 and XP support using GPIO
lines as PWM lines. For example the Armada 38x family has the same
hardware support. As such "marvell,armada-370-xp-gpio" for the
compatible string is a misnomer.

Change the compatible string to "marvell,armada-370-gpio" before the
driver makes it out of the -rc stage. This also follows the practice of
using only the first device family supported as part of the name.

Also update the documentation and comments in the code accordingly.

Fixes: 757642f9 ("gpio: mvebu: Add limited PWM support")
Signed-off-by: NRalph Sennhauser <ralph.sennhauser@gmail.com>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The Armada 7K and 8K SoCs use the same gpio controller as most of the
other mvebu SoCs. However, the main difference is that the GPIO
controller is part of a bigger system controller, and a syscon is used to
control the overall system controller. Therefore, the driver needs to be
adjusted to retrieve the regmap of the syscon to access registers, and
account for the fact that registers are located at a certain offset
within the regmap.

This commit add the support of the syscon and introduce a new variant for
this case.

It was based on the preliminary work of Thomas Petazzoni.
Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

In some place in the driver regmap_update_bits was misused. Indeed the
last argument is not the value of the bit (or group of bits) itself but
the mask value inside the register.

So when setting the bit N, then the value must be BIT(N) and not 1.

CC: Ralph Sennhauser <ralph.sennhauser@gmail.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: NRalph Sennhauser <ralph.sennhauser@gmail.com>
Tested-by: NChris Packham <Chris.Packham@alliedtelesis.co.nz>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

If more than one gpio bank has the "pwm" property, only one will be
registered successfully, all the others will fail with:
mvebu-gpio: probe of f1018140.gpio failed with error -17

That's because in alloc_pwms(), the chip->base (aka "int pwm"), was not
set (thus, ==0) ; and 0 is a meaningful start value in alloc_pwm().
What was intended is mvpwm->chip->base = -1.
Like that, the numbering will be done auto-magically

Moreover, as the region might be already occupied by another pwm, we
shouldn't force:
mvpwm->chip->base = 0
nor
mvpwm->chip->base = id * MVEBU_MAX_GPIO_PER_BANK;

Tested on clearfog-pro (Marvell 88F6828)

Fixes: 757642f9 ("gpio: mvebu: Add limited PWM support")
Signed-off-by: NRichard Genoud <richard.genoud@gmail.com>
Reviewed-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The blink counter A was always selected because 0 was forced in the
blink select counter register.
The variable 'set' was obviously there to be used as the register value,
selecting the B counter when id==1 and A counter when id==0.

Tested on clearfog-pro (Marvell 88F6828)

Fixes: 757642f9 ("gpio: mvebu: Add limited PWM support")
Reviewed-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: NRalph Sennhauser <ralph.sennhauser@gmail.com>
Signed-off-by: NRichard Genoud <richard.genoud@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

In order to be able to use this driver with the Armada 7K/8K SoCs, we
need to use the regmap to access the registers. Indeed for these new SoCs,
the gpio node will be part of a syscon.

[gregory.clement@free-electrons.com:
 - fixed merge conflcit from 4.10 to 4.12-rc1
 - added a commit log]
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This commit sorts alphabetically the header files.
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Armada 370/XP devices can 'blink' GPIO lines with a configurable on
and off period. This can be modelled as a PWM.

However, there are only two sets of PWM configuration registers for
all the GPIO lines. This driver simply allows a single GPIO line per
GPIO chip of 32 lines to be used as a PWM. Attempts to use more return
EBUSY.

Due to the interleaving of registers it is not simple to separate the
PWM driver from the GPIO driver. Thus the GPIO driver has been
extended with a PWM driver.
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
URL: https://patchwork.ozlabs.org/patch/427287/
URL: https://patchwork.ozlabs.org/patch/427295/
[Ralph Sennhauser:
  * Port forward
  * Merge PWM portion into gpio-mvebu.c
  * Switch to atomic PWM API
  * Add new compatible string marvell,armada-370-xp-gpio
  * Update and merge documentation patch
  * Update MAINTAINERS]
Signed-off-by: NRalph Sennhauser <ralph.sennhauser@gmail.com>
Tested-by: NAndrew Lunn <andrew@lunn.ch>
Acked-by: NThierry Reding <thierry.reding@gmail.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Use the BIT macro instead of explicitly shifting bits for some added
clarity.
Signed-off-by: NRalph Sennhauser <ralph.sennhauser@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

A modern compiler should know better when to inline, so drop the inline
keywords.
Signed-off-by: NRalph Sennhauser <ralph.sennhauser@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Fix whitespace errors missed by checkpatch.
Signed-off-by: NRalph Sennhauser <ralph.sennhauser@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Fix whitespace errors reported by checkpatch.
Signed-off-by: NRalph Sennhauser <ralph.sennhauser@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Use unsigned int instead of plain unsigned as reported by checkpatch.
Signed-off-by: NRalph Sennhauser <ralph.sennhauser@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

While this isn't an issue according to checkpatch two styles are used.
Add a blank line to the block comments missing a blank line at the start
so multiline block comments look the same across the file.
Signed-off-by: NRalph Sennhauser <ralph.sennhauser@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Fix issues in block comments reported by checkpatch.
Signed-off-by: NRalph Sennhauser <ralph.sennhauser@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Casting a pointer to an int is not portable, and provokes a compiler
warning.  Cast to unsigned long instead to avoid the warning.

drivers/gpio/gpio-mvebu.c: In function 'mvebu_gpio_probe':
drivers/gpio/gpio-mvebu.c:662:17: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
   soc_variant = (int) match->data;
                 ^

This will be needed when building gpio-mvebu for Armada 7k/8k ARM64
SoCs.
Signed-off-by: NRussell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This fixes the irq allocation in this driver to not print:
 irq: Cannot allocate irq_descs @ IRQ34, assuming pre-allocated
 irq: Cannot allocate irq_descs @ IRQ66, assuming pre-allocated

Which happens because the driver already called irq_alloc_descs()
and so the change to use irq_domain_add_simple resulted in calling
irq_alloc_descs() twice.

Modernize the irq allocation in this driver to use the
irq_domain_add_linear flow directly and eliminate the use of
irq_domain_add_simple/legacy

Fixes: ce931f57 ("gpio/mvebu: convert to use irq_domain_add_simple()")
Signed-off-by: NJason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The Kconfig currently controlling compilation of this code is:

drivers/gpio/Kconfig:config GPIO_MVEBU
drivers/gpio/Kconfig:   def_bool y

...meaning that it currently is not being built as a module by anyone.

Lets remove the couple traces of modularity so that when reading the
driver there is no doubt it is builtin-only.

Since module_platform_driver() uses the same init level priority as
builtin_platform_driver() the init ordering remains unchanged with
this commit.

Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.

Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Use devm_gpiochip_add_data() for GPIO registration and clean the
error path.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>

This makes the driver use the data pointer added to the gpio_chip
to store a pointer to the state container instead of relying on
container_of().

Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The name .dev in a struct is normally reserved for a struct device
that is let us say a superclass to the thing described by the struct.
struct gpio_chip stands out by confusingly using a struct device *dev
to point to the parent device (such as a platform_device) that
represents the hardware. As we want to give gpio_chip:s real devices,
this is not working. We need to rename this member to parent.

This was done by two coccinelle scripts, I guess it is possible to
combine them into one, but I don't know such stuff. They look like
this:

@@
struct gpio_chip *var;
@@
-var->dev
+var->parent

and:

@@
struct gpio_chip var;
@@
-var.dev
+var.parent

and:

@@
struct bgpio_chip *var;
@@
-var->gc.dev
+var->gc.parent

Plus a few instances of bgpio that I couldn't figure out how
to teach Coccinelle to rewrite.

This patch hits all over the place, but I *strongly* prefer this
solution to any piecemal approaches that just exercise patch
mechanics all over the place. It mainly hits drivers/gpio and
drivers/pinctrl which is my own backyard anyway.

Cc: Haavard Skinnemoen <hskinnemoen@gmail.com>
Cc: Rafał Miłecki <zajec5@gmail.com>
Cc: Richard Purdie <rpurdie@rpsys.net>
Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Cc: Alek Du <alek.du@intel.com>
Cc: Jaroslav Kysela <perex@perex.cz>
Cc: Takashi Iwai <tiwai@suse.com>
Acked-by: NDmitry Torokhov <dmitry.torokhov@gmail.com>
Acked-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: NLee Jones <lee.jones@linaro.org>
Acked-by: NJiri Kosina <jkosina@suse.cz>
Acked-by: NHans-Christian Egtvedt <egtvedt@samfundet.no>
Acked-by: NJacek Anaszewski <j.anaszewski@samsung.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Replace all trivial request/free callbacks that do nothing but call into
pinctrl code with the generic versions.
Signed-off-by: NJonas Gorski <jogo@openwrt.org>
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NJames Hogan <james.hogan@imgtec.com>
Acked-by: NStefan Agner <stefan@agner.ch>
Acked-by: NJoachim Eastwood <manabian@gmail.com>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Most interrupt flow handlers do not use the irq argument. Those few
which use it can retrieve the irq number from the irq descriptor.

Remove the argument.

Search and replace was done with coccinelle and some extra helper
scripts around it. Thanks to Julia for her help!
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Cc: Julia Lawall <Julia.Lawall@lip6.fr>
Cc: Jiang Liu <jiang.liu@linux.intel.com>

The irq argument of most interrupt flow handlers is unused or merily
used instead of a local variable. The handlers which need the irq
argument can retrieve the irq number from the irq descriptor.

Search and update was done with coccinelle and the invaluable help of
Julia Lawall.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Cc: Julia Lawall <Julia.Lawall@lip6.fr>
Cc: Jiang Liu <jiang.liu@linux.intel.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: linux-gpio@vger.kernel.org

Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc while we
already have a pointer to corresponding irq_desc.

Preparatory patch for the removal of the 'irq' argument from irq flow
handlers.
Signed-off-by: NJiang Liu <jiang.liu@linux.intel.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Cc: Alexandre Courbot <gnurou@gmail.com>
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Chained irq handlers usually set up handler data as well. We now have
a function to set both under irq_desc->lock. Replace the two calls
with one.

Search and conversion was done with coccinelle:
Reported-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Cc: Julia Lawall <Julia.Lawall@lip6.fr>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: linux-gpio@vger.kernel.org

Level IRQ handlers and edge IRQ handler are managed by tow different
sets of registers. But currently the driver uses the same mask for the
both registers. It lead to issues with the following scenario:

First, an IRQ is requested on a GPIO to be triggered on front. After,
this an other IRQ is requested for a GPIO of the same bank but
triggered on level. Then the first one will be also setup to be
triggered on level. It leads to an interrupt storm.

The different kind of handler are already associated with two
different irq chip type. With this patch the driver uses a private
mask for each one which solves this issue.

It has been tested on an Armada XP based board and on an Armada 375
board. For the both boards, with this patch is applied, there is no
such interrupt storm when running the previous scenario.

This bug was already fixed but in a different way in the legacy
version of this driver by Evgeniy Dushistov:
9ece8839 "ARM: orion: Fix for certain
sequence of request_irq can cause irq storm". The fact the new version
of the gpio drive could be affected had been discussed there:
http://thread.gmane.org/gmane.linux.ports.arm.kernel/344670/focus=364012Reported-by: NEvgeniy A. Dushistov <dushistov@mail.ru>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.7 +
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Ensure that when there is an error during probe that the gpiochip is
removed and the generic irq chip is removed.
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Wrap some long lines.
Prefer seq_puts() over seq_printf().
space to tab conversions.
Spelling error fix.
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This commit adds the implementation of ->suspend() and ->resume()
platform_driver hooks in order to save and restore the state of the
GPIO configuration. In order to achieve that, additional fields are
added to the mvebu_gpio_chip structure.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

A platform_driver does not need to set an owner, it will be populated by the
driver core.
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

There's no reason to use an initcall to initialize this driver,
and regular module_platform_driver() can be used instead.
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Reviewed-by: NJavier Martinez Canillas <javier@dowhile0.org>
Acked-by: NJason Cooper <jason@lakedaemon.net>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Make of_device_id array const, because all OF functions
handle it as const.
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Acked-by: NJason Cooper <jason@lakedaemon.net>
Reviewed-by: NJavier Martinez Canillas <javier@dowhile0.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

On currently supported SoCs, the GPIO block used on Marvell EBU SoCs
is always connected to the Marvell MPIC. However, we are going to
introduce the support for newer Marvell EBU SoCs that use the
Cortex-A9 core, and therefore use the GIC as their main interrupt
controller, to which the GPIO block controlled by the gpio-mvebu
driver is connected.

The GIC interrupt controller driver uses the fasteoi flow handler. In
order to ensure that the eoi hook of the GIC driver gets called, the
GPIO driver should call chained_irq_enter() and chained_irq_exit() in
its handler. Without this, the first GPIO interrupt locks up the
system because it doesn't get acked at the GIC level.

This change is similar to for example commit
0d978eb7 ("gpio: davinci: use
chained_irq_enter/chained_irq_exit API").
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NJason Cooper <jason@lakedaemon.net>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Return the appropriate error code instead of hardcoding it.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This switches the two members of struct gpio_chip that were
defined as unsigned foo:1 to bool, because that is indeed what
they are. Switch all users in the gpio and pinctrl subsystems
to assign these values with true/false instead of 0/1. The
users outside these subsystems will survive since true/false
is 1/0, atleast we set some kind of more strict typing example.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

There is a bug in mvebu_gpio_probe() where we do:

	mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1);
	if (mvchip->irqbase < 0) {

The problem is that mvchip->irqbase is unsigned so the error handling
doesn't work.  I have changed it to be a regular int.

Cc: stable@vger.kernel.org
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Remove unneeded error handling on the result of a call to
platform_get_resource when the value is passed to devm_ioremap_resource.

Move the call to platform_get_resource adjacent to the call to
devm_ioremap_resource to make the connection between them more clear.

A simplified version of the semantic patch that makes this change is as
follows: (http://coccinelle.lip6.fr/)

// <smpl>
@@
expression pdev,res,n,e,e1;
expression ret != 0;
identifier l;
@@

- res = platform_get_resource(pdev, IORESOURCE_MEM, n);
  ... when != res
- if (res == NULL) { ... \(goto l;\|return ret;\) }
  ... when != res
+ res = platform_get_resource(pdev, IORESOURCE_MEM, n);
  e = devm_ioremap_resource(e1, res);
// </smpl>
Signed-off-by: NJulia Lawall <Julia.Lawall@lip6.fr>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Use irq_get_trigger_type() to get the IRQ trigger type flags
instead calling irqd_get_trigger_type(irq_get_irq_data(irq))
Signed-off-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: NGrant Likely <grant.likely@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Samuel Ortiz <sameo@linux.intel.com>
Acked-by: NJason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-mips@linux-mips.org
Link: http://lkml.kernel.org/r/1371228049-27080-3-git-send-email-javier.martinez@collabora.co.ukSigned-off-by: NThomas Gleixner <tglx@linutronix.de>