With the clock driver upstream, switch to the real clock.
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Add the SoC-level description of the PCIe controller found on the Marvell
Armada 3700 and enable this PCIe controller on the development board for
this SoC.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Added mdio node for mdio driver.  Also added phy-handle
reference to the ethernet nodes.

Removed unused clock node from storm sgenet1.
Signed-off-by: NIyappan Subramanian <isubramanian@apm.com>
Tested-by: NFushen Chen <fchen@apm.com>
Tested-by: NToan Le <toanle@apm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Signed-off-by: NThierry Reding <treding@nvidia.com>

The sor1 IP block needs the sor1_src clock to configure the clock tree
depending on whether it's running in HDMI or DP mode.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Tegra210 XUSB subsystem has 3 power partitions which are XUSBA
(super-speed logic), XUSBB (USB device logic) and XUSBC (USB host
logic). Populate the device-tree nodes for these XUSB partitions.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add the DPAUX pinctrl states for the DPAUX nodes defining all three
possible states of "aux", "i2c" and "off". Also add the 'i2c-bus'
node for the DPAUX nodes so that the I2C driver core does not attempt
to parse the pinctrl state nodes.

Populate the nodes for the pinctrl clients of the DPAUX pin controller.
There are two clients for each DPAUX instance, namely the SOR and one of
the I2C adapters. The SOR clients may used the DPAUX pins in either AUX
or I2C modes and so for these devices we don't define any of the generic
pinctrl states (default, idle, etc) because the SOR driver will directly
set the state needed. For I2C clients only the I2C mode is used and so
we can simplify matters by using the generic pinctrl states for default
and idle.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add the ACONNECT bus node for Tegra210 which is used to interface to
the various devices in the Audio Processing Engine (APE).
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add the audio powergate for Tegra210.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add regulators to the Tegra210 Smaug DTS file including support for the
MAX77620 PMIC.
Signed-off-by: NRhyland Klein <rklein@nvidia.com>
Acked-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The XUSB mailbox interrupt for Tegra210 is 40 and not 49 which is for
the XUSB pad controller. For some Tegra210 boards, this is causing USB
connect and disconnect events to go undetected. Fix this by changing the
interrupt number for the XUSB mailbox to 40.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Enable the XUSB controller on Jetson TX1. One of the USB 3.0 lanes goes
to an internal ethernet interface, while a second USB 3.0 lane supports
the USB-A receptacle on the I/O board.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add a chosen node to the device tree that contains a stdout-path
property which defines the debug serial port.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add a device tree node for the Tegra XUSB controller. It contains a
phandle to the XUSB pad controller for control of the PHYs assigned
to the USB ports.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add a device tree node for the XUSB pad controller found on Tegra210.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Some variants of the Jetson TX1 ship with a 8.0" WUXGA TFT LCD panel
connected via four DSI lanes.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add power supplies for the SD/MMC card slot. Note that vmmc-supply is
currently restricted to 3.3 V because we don't support switching the
mode yet.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add a device tree node for the MAX77620 PMIC found on the p2180
processor module (Jetson TX1). Also add supporting power supplies,
such as the main 5 V system supply.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add video encoder node for MT8173
Signed-off-by: NTiffany Lin <tiffany.lin@mediatek.com>
Signed-off-by: NHans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: NMauro Carvalho Chehab <mchehab@s-opensource.com>

Add VPU drivers for MT8173
Signed-off-by: NAndrew-CT Chen <andrew-ct.chen@mediatek.com>
Signed-off-by: NTiffany Lin <tiffany.lin@mediatek.com>
Signed-off-by: NHans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: NMauro Carvalho Chehab <mchehab@s-opensource.com>

This reverts commit f3abd629, which caused a build regression:

arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi:48:41: fatal error: dt-bindings/clock/gxbb-clkc.h: No such file or directory

We should apply this patch one merge window later, once the clk branch
is merged as well.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add pl031 rtc0 and rtc1 support to hi6220 dtsi

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Wei Xu <xuwei5@hisilicon.com>
Cc: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org>
[jstultz: Forward ported and tweaked commit description,
 added rtc1 entry as suggested by Guodong]
Signed-off-by: NJohn Stultz <john.stultz@linaro.org>
Signed-off-by: NWei Xu <xuwei5@hisilicon.com>

Enable the Watchdog Timer (WDT) controller on the Renesas Salvator-X
board equipped with an R-Car M3-W (r8a7796) SoC.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add a device node for the Watchdog Timer (WDT) controller on the Renesas
R-Car M3-W (r8a7796) SoC.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Hook up all devices that are part of the CPG/MSSR Clock Domain to the
SYSC "always-on" PM Domain, for a more consistent device-power-area
description in DT.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add a device node for the System Controller.
Hook up the Cortex-A57 CPU core and L2 cache/SCU to their respective PM
Domains.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This patch adds initial board support for R8A7796 Salvator-X.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Basic support for the Gen 3 R-Car M3-W SoC.

Based on work for the r8a7795 and r8a7796 SoCs by
Takeshi Kihara, Dirk Behme and Geert Uytterhoeven.
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Adds CAN FD controller node for r8a7795.

Note: CAN FD controller register base address specified in R-Car Gen3
Hardware User Manual v0.5E is incorrect. The correct address is:

CAN FD - 0xe66c0000
Signed-off-by: NRamesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

For consistency with a57_0/a57_1 cpu nodes, and all other nodes.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Change the BUCK2 (vdd_atlas) voltage range to '500 - 1200mv' since
CPU DVFS requires it.
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>

Add two new blocks of clocks. The peripheral clocks are the source clocks
of the peripheral of the Armada 3700 SoC.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

Add a new block of clocks. The Time Base Generators clocks can be the
parent of the peripheral clocks.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

The configuration of the clock depend of the gpio latch. This information
is stored in the gpio block registers. That's why the block is shared
using a syscon node.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

This adds basic chip support for MT6755 SoC.
Signed-off-by: NMars Cheng <mars.cheng@mediatek.com>
Signed-off-by: NMatthias Brugger <matthias.bgg@gmail.com>

This commit adds the Device Tree description for the two XOR engines
found in the CP part of the Armada 7K/8K SoC.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

As suggested by Rob Herring, we should:

 1/ Use a SoC-specific compatible string in addition to the more generic
    one.

 2/ The generic compatible string has been changed from
    "marvell,mv-xor-v2" to "marvell,xor-v2".

We simply reflect the changes made to the Device Tree bindings to the
relevant Marvell 7K/8K Device Tree files.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

Add media subsystem reset dts support.
Signed-off-by: NChen Feng <puck.chen@hisilicon.com>
Signed-off-by: NXinliang Liu <xinliang.liu@linaro.org>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

This names the GPIO lines on the HiKey board in accordance with
the 96Board Specification for especially the Low Speed External
Connector: "GPIO-A" thru "GPIO-L".

This will make these line names reflect through to userspace
so that they can easily be identified and used with the new
character device ABI.

Some care has been taken to name all lines, not just those used
by the external connectors, also lines that are muxed into some
other function than GPIO: these are named "[FOO]" so that users
can see with lsgpio what all lines are used for.

Cc: devicetree@vger.kernel.org
Cc: John Stultz <john.stultz@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Cc: David Mandala <david.mandala@linaro.org>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NWei Xu <xuwei5@hisilicon.com>