Do not leak memory and free irqs in case of an error.
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NDavid Dueck <davidcdueck@googlemail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

If stm32f4_rcc_lookup() is called with primary == 0 and secondary == 192
then it will read beyond the end of the table array due to an out-by-one
error in the range check.

In addition to the fixing the inequality we also modify the r.h.s. to
make it even more explicit that we are comparing against the size of
table in bits.
Reported-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NDaniel Thompson <daniel.thompson@linaro.org>
Acked-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>
Fixes: 358bdf89 ("clk: stm32: Add clock driver for STM32F4[23]xxx devices")
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

A 32-bit variable should be type casted to 64-bit before arithmetic
operation and assigning it to a 64-bit variable
Reported-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NRay Jui <rjui@broadcom.com>
Fixes: 5fe225c1 ("clk: iproc: add initial common clock support")
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

of_property_read_string_index takes array of pointers and assign them to
strings read from device tree property. No additional memory allocation
is needed prior to calling of_property_read_string_index. In fact, since
the array of pointers will be re-assigned to other strings, any memory
that it points to prior to calling of_property_read_string_index will be
leaked
Reported-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NRay Jui <rjui@broadcom.com>
Fixes: 5fe225c1 ("clk: iproc: add initial common clock support")
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The driver supports decoding and statically modelling PLL state (i.e.
we inherit state from bootloader) and provides support for all
peripherals that support simple one-bit gated clocks. The covers all
peripherals whose clocks come from the AHB, APB1 or APB2 buses.

It has been tested on an STM32F429I-Discovery board. The clock counts
for TIM2, USART1 and SYSTICK are all set correctly and the wall clock
looks OK when checked with a stopwatch. I have also tested a prototype
driver for the RNG hardware. The RNG clock is correctly enabled by the
framework (also did inverse test and proved that by changing DT to
configure the wrong clock bit then we observe the RNG driver to fail).
Signed-off-by: NDaniel Thompson <daniel.thompson@linaro.org>
Reviewed-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>
[sboyd@codeaurora.org: Silence sparse warnings]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Exynos4210 based platforms have switched over to use generic
cpufreq driver for cpufreq functionality. So the Exynos
specific cpufreq support for these platforms can be removed.

Changes by Bartlomiej:
- dropped Exynos5250 support removal for now
- updated exynos-cpufreq.[c,h]

Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NThomas Abraham <thomas.ab@samsung.com>
Signed-off-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos4210.

Changes by Bartlomiej:
- fixed issue with wrong dividers being setup by Common Clock Framework
  (by an addition of CLK_RECALC_NEW_RATES clock flag to mout_apll clock,
  without this change cpufreq-dt driver showed ~10 mA larger energy
  consumption when compared to cpufreq-exynos one when "performance"
  cpufreq governor was used on Exynos4210 SoC based Origen board), this
  was probably meant to be workarounded by use of CLK_GET_RATE_NOCACHE
  and CLK_DIVIDER_READ_ONLY clock flags in the original patchset (in
  "[PATCH v12 6/6] clk: samsung: remove unused clock aliases and update
  clock flags") but using these flags is not sufficient to fix the issue
  observed
- removed Exynos5250 and Exynos5420 support for now

Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: NThomas Abraham <thomas.ab@samsung.com>
Signed-off-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

The CPU clock provider supplies the clock to the CPU clock domain. The
composition and organization of the CPU clock provider could vary among
Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers
and gates. This patch defines a new clock type for CPU clock provider and
adds infrastructure to register the CPU clock providers for Samsung
platforms.

Changes by Bartlomiej:
- fixed issue with setting lower dividers before the parent clock speed
  was lowered (the issue resulted in lockup on Exynos4210 SoC based
  Origen board when "ondemand" cpufreq governor was stress tested)
- fixed missing spin_unlock on error in exynos_cpuclk_post_rate_change()
  problem by moving cfg_data search outside of the spin locked area
- removed leftover kfree() in exynos_register_cpu_clock() that could
  result in dereferencing the NULL pointer on error
- moved spin_lock earlier in exynos_cpuclk_pre_rate_change() to cover
  reading of E4210_SRC_CPU and E4210_DIV_CPU1 registers
- added missing "last chance" checks to wait_until_divider_stable() and
  wait_until_mux_stable() (needed in case that IRQ handling took long
  time to proceed and resulted in function printing incorrect error
  message about timeout)
- moved E4210_CPU_DIV[0,1]() macros just before their only users,
  this resulted in moving them from patch #2 to patch #3/6 ("clk:
  samsung: exynos4: add cpu clock configuration data and instantiate
  cpu clock")
- removed E5250_CPU_DIV[0,1](), E5420_EGL_DIV0() and E5420_KFC_DIV()
  macros for now
- added my Copyrights to drivers/clk/samsung/clk-cpu.c

Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: NThomas Abraham <thomas.ab@samsung.com>
Signed-off-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

This flag is needed to fix the issue with wrong dividers being setup
by Common Clock Framework when using the new Exynos cpu clock support.

The issue happens because clk_core_set_rate_nolock()  calls
clk_calc_new_rates(clk, rate) before both pre/post clock notifiers have
a chance to run.  In case of Exynos cpu clock support pre/post clock
notifiers are registered for mout_apll clock which is a parent of armclk
cpu clock and dividers are modified in both pre and post clock notifier.
This results in wrong dividers values being later programmed by
clk_change_rate(top).  To workaround the problem CLK_RECALC_NEW_RATES
flag is added and it is set for mout_apll clock later so the correct
divider values are re-calculated after both pre and post clock notifiers
had run.

For example when using "performance" governor on Exynos4210 Origen board
the cpufreq-dt driver requests to change the frequency from 1000MHz to
1200MHz and after the change state of the relevant clocks is following:

Without use of CLK_GET_RATE_NOCACHE flag:

 fout_apll rate: 1200000000
         fout_apll_div_2 rate: 600000000
                 mout_clkout_cpu rate: 600000000
                         div_clkout_cpu rate: 600000000
                                 clkout_cpu rate: 600000000
         mout_apll rate: 1200000000
                 armclk rate: 1200000000
                 mout_hpm rate: 1200000000
                         div_copy rate: 300000000
                                 div_hpm rate: 300000000
                 mout_core rate: 1200000000
                         div_core rate: 1200000000
                                 div_core2 rate: 1200000000
                                         arm_clk_div_2 rate: 600000000
                                         div_corem0 rate: 300000000
                                         div_corem1 rate: 150000000
                                         div_periph rate: 300000000
                         div_atb rate: 300000000
                                 div_pclk_dbg rate: 150000000
                 sclk_apll rate: 1200000000
                         sclk_apll_div_2 rate: 600000000

With use of CLK_GET_RATE_NOCACHE flag:

 fout_apll rate: 1200000000
         fout_apll_div_2 rate: 600000000
                 mout_clkout_cpu rate: 600000000
                         div_clkout_cpu rate: 600000000
                                 clkout_cpu rate: 600000000
         mout_apll rate: 1200000000
                 armclk rate: 1200000000
                 mout_hpm rate: 1200000000
                         div_copy rate: 200000000
                                 div_hpm rate: 200000000
                 mout_core rate: 1200000000
                         div_core rate: 1200000000
                                 div_core2 rate: 1200000000
                                         arm_clk_div_2 rate: 600000000
                                         div_corem0 rate: 300000000
                                         div_corem1 rate: 150000000
                                         div_periph rate: 300000000
                         div_atb rate: 240000000
                                 div_pclk_dbg rate: 120000000
                 sclk_apll rate: 150000000
                         sclk_apll_div_2 rate: 75000000

Without this change cpufreq-dt driver showed ~10 mA larger energy
consumption when compared to cpufreq-exynos one when "performance"
cpufreq governor was used on Exynos4210 SoC based Origen board.

This issue was probably meant to be workarounded by use of
CLK_GET_RATE_NOCACHE and CLK_DIVIDER_READ_ONLY clock flags in
the original Exynos cpu clock patchset (in "[PATCH v12 6/6] clk:
samsung: remove unused clock aliases and update clock flags" patch)
but usage of these flags is not sufficient to fix the issue observed.

Cc: Thomas Abraham <thomas.ab@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

Add driver for NXP LPC18xx/43xx Clock Control Unit (CCU). The CCU
provides fine grained gating of most clocks present in the SoC.
Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

Add driver for NXP LPC18xx/43xx Clock Generation Unit (CGU). The CGU
contains several clock generators and output stages that route the
clocks either directly to peripherals or to a Clock Control Unit
(CCU).
Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

Main PLL controller has post divider bits in a separate register in
pll controller. Use the value from this register instead of fixed
divider when available.
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

The crypto SRAM, used by the armada 370 cpuidle code to workaround a bug
in the BootROM code, requires the crypto clk to be up and running.
Flag the crypto clk as IGNORE_UNUSED until we add the proper
infrastructure to define the crypto SRAM in the DT and reference the crypto
clk in this SRAM node.
Reported-by: NKevin Hilman <khilman@linaro.org>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: NKevin Hilman <khilman@linaro.org>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

The Broadcom Cygnus SoC is architected under the iProc architecture. It
has the following PLLs: ARMPLL, GENPLL, LCPLL0, MIPIPLL, all dervied
from an onboard crystal. Cygnus also has various ASIU clocks that are
derived directly from the onboard crystal.
Signed-off-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

The clock code under drivers/clk/bcm now contains code for both the
Broadcom mobile SoCs and the iProc SoCs. Change the the makefile
dependency to be under config flag CONFIG_ARCH_BCM that's enabled for
both families of SoCs
Signed-off-by: NRay Jui <rjui@broadcom.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

This adds basic and generic support for various iProc PLLs and clocks
including the ARMPLL, GENPLL, LCPLL, MIPIPLL, and ASIU clocks.

SoCs under the iProc architecture can define their specific register
offsets and clock parameters for their PLL and clock controllers. These
parameters can be passed as arugments into the generic iProc PLL and
clock setup functions

Derived from code originally provided by Jonathan Richardson
<jonathar@broadcom.com>
Signed-off-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

This error handling hopefully isn't needed but it make the static
checkers happy.
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Acked-by: NCarlo Caione <carlo@endlessm.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

A recent change to mark parent names as const missed this struct
member so we get warnings like:

drivers/clk/pxa/clk-pxa25x.c:122:2: warning: initialization
discards 'const' qualifier from pointer target type

Fix it.
Reported-by: Nkbuild test robot <fengguang.wu@intel.com>
Acked-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The debug_node field is only used when DEBUG_FS config is selected,
so declare it only if DEBUG_FS is selected.
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Currently it is not made explicit why clk_fixed_set_rate() can ignore
its arguments and unconditionally return success. Add a comment
to explain this.

We also mark the clk_ops table const since it should never be
modified at runtime.
Suggested-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDaniel Thompson <daniel.thompson@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

drivers/clk/clk-cdce925.c:550: warning: format ‘%u’ expects type
‘unsigned int’, but argument 6 has type ‘size_t’

Cc: Mike Looijmans <mike.looijmans@topic.nl>
Reported-by: Nkbuild test robot <fengguang.wu@intel.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This line was indented too far.
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Acked-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

This patch adds 'CLK_IGNORE_UNUSED' flag to clocks which is required for
operation of secure monitor call (smc). System will hang when it executes 'smc'
with one of those clock is gated. All related clocks must be enabled.
Signed-off-by: NJonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

This patch adds the CLK_SET_RATE_PARENT flag for 'aclk_g3d' clock and parent
clocks becuase 'aclk_g3d' is used to change GPU frequency for DVFS (Dynamic
Voltage Frequency Scaling) feature and adds CLK_IGNORE_UNUSED flags to
'aclk_asyncapbs_g3d'/'aclk_asyncapbm_g3d' clocks to access the SFR
of the MALI device.
Signed-off-by: NJoonyoung Shim <jy0922.shim@samsung.com>
[cw00.choi: Add patch description and add CLK_SET_RATE_PARENT to 'aclk_g3d' clk]
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

This DIV_CPIF register must be stored when the system is suspended, and must
be restored on system resume. This patch adds the register to the list of
restored registers.
Signed-off-by: NHyungwon Hwang <human.hwang@samsung.com>
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

This patch adds CLK_SET_RATE_PARENT flag to support DVFS of Cortex-{A53|A57}
core (big.LITTLE core) because 'sclk_{apollo|atlas}' leaf clock is used to
change the CPU frequency of Cortex-{A53|A57} core in arm_big_little.c driver.
- 'apollo' word means the LITTLE core (Cortex-A53 core) in Exynos5433 TRM.
- 'atlas' word means the big core (Cortex-A57 core) in Exynos5433 TRM.
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Use of_clk_parent_fill to fill in the parent clock's array.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Sprinkled all through the platform clock drivers are code like this to
fill the clock parent array:

for (i = 0; i < num_parents; ++i)
	parent_names[i] = of_clk_get_parent_name(np, i);

The of_clk_parent_fill() will do the same as the code above, and while
at it, return the number of parents as well since the logic of the
function is to the walk the clock node to look for the parent.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
[sboyd@codeaurora.org: Fixed kernel-doc]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

I've had reports of UEFI platforms failing iSCSI boot in various
configurations, that ended up being caused by network initialization
scripts getting tripped up by unexpected null addresses (0.0.0.0) being
reported for gateways, dhcp servers, and dns servers.

The tianocore EDK2 iSCSI driver generates an iBFT table that always uses
IPv4-mapped IPv6 addresses for the NIC structure fields.  This results
in values that are "not present or not specified" being reported as
::ffff:0.0.0.0 rather than all zeros as specified.

The iscsi_ibft module filters unspecified fields from the iBFT from
sysfs, preventing userspace from using invalid values and making it easy
to check for the presence of a value.  This currently fails in regard to
these mapped null addresses.

In order to remain consistent with how the iBFT information is exposed,
we should accommodate the behavior of the tianocore iSCSI driver as it's
already in the wild in a large number of servers.

Tested under qemu using an OVMF build of tianocore EDK2.
Signed-off-by: NChris Leech <cleech@redhat.com>
Reviewed-by: NMike Christie <michaelc@cs.wisc.edu>
Signed-off-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>

This patch adds support for the basic clocks found on the Amlogic
Meson8b SoCs.
Signed-off-by: NCarlo Caione <carlo@endlessm.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patchset adds the infrastructure for registering and managing the
core clocks found on Amlogic MesonX SoCs. In particular:

- PLLs
- CPU clock
- Fixed rate clocks, fixed factor clocks, ...
Signed-off-by: NCarlo Caione <carlo@endlessm.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Writing to a file is supposed to return the number of bytes written.
Returning zero unfortunately causes bash to constantly spin trying
to write to the sysfs file, to such an extent that even ^c and ^z
have no effect.  The only way out of that is to kill the shell and
log back in.  This isn't nice behaviour.

Fix it by returning the number of characters written to sysfs files.

[airlied: used suggestion from Al Viro]
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NDave Airlie <airlied@redhat.com>

On some v7 devices (e.g. Lenovo-E550) the deltas reported are typically
only in the 0-1 range dividing this by 2 results in a range of 0-0.

And even for v7 devices where this does not lead to making the trackstick
entirely unusable, it makes it twice as slow as before we added v7 support
and were using the ps/2 mouse emulation of the dual point setup.

If some kind of generic slowdown is actually necessary for some devices,
then that belongs in userspace, not in the kernel.

Cc: stable@vger.kernel.org
Reported-and-tested-by: NRico Moorman <rico.moorman@gmail.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Reviewed-by: NBenjamin Tissoires <benjamin.tissoires@gmail.com>
Signed-off-by: NDmitry Torokhov <dmitry.torokhov@gmail.com>

This adds new icbody type to the list recognized by Elantech PS/2 driver.

Cc: stable@vger.kernel.org
Signed-off-by: NSam Hung <sam.hung@emc.com.tw>
Signed-off-by: NDmitry Torokhov <dmitry.torokhov@gmail.com>

"IS_ENABLED(PPC_PSERIES)" always evaluates to false, as IS_ENABLED() is
supposed to be used with the full Kconfig symbol name, including the
"CONFIG_" prefix.

Add the missing "CONFIG_" prefix to fix this.

Fixes: a25095d4 ("of: Move dynamic node fixups out of powerpc and into common code")
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Cc: stable@vger.kernel.org #+3.17
Signed-off-by: NGrant Likely <grant.likely@linaro.org>

Since commit 2893c379 ("clk: make strings in parent name arrays
const") the name of parent clocks can be const. So add more const in
several clock drivers.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Added the USB serial device ID for the HubZ dual ZigBee
and Z-Wave radio dongle.
Signed-off-by: NJohn D. Blair <johnb@candicontrols.com>
Cc: stable <stable@vger.kernel.org>
Signed-off-by: NJohan Hovold <johan@kernel.org>

The size of clk_data should be the same as CLK_APMIXED_NR_CLK
instead of ARRAY_SIZE(plls). CLK_APMIXED_* is numbered from 1, so
CLK_APMIXED_NR_CLK will be greater than ARRAY_SIZE(plls).
Signed-off-by: NJames Liao <jamesjj.liao@mediatek.com>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>