- 16 11月, 2012 1 次提交
-
-
由 Will Deacon 提交于
The LOCKSTATUS register for memory-mapped coresight devices indicates whether or not the device in question implements hardware locking. If not, locking is not present (i.e. LSR.SLI == 0) and LAR is write-ignore, so software doesn't actually need to check the status register at all. This patch removes the broken LSR checks. Cc: Ming Lei <ming.lei@canonical.com> Reported-by: NMike Williams <michael.williams@arm.com> Signed-off-by: NWill Deacon <will.deacon@arm.com>
-
- 02 12月, 2011 1 次提交
-
-
由 Ming Lei 提交于
OMAP4 uses cross trigger interface(CTI) to route performance monitor irq to GIC, so introduce cti helpers to make access for cti easily. Acked-by: NJean Pihet <j-pihet@ti.com> Signed-off-by: NMing Lei <ming.lei@canonical.com> Signed-off-by: NWill Deacon <will.deacon@arm.com>
-