- 16 8月, 2015 2 次提交
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由 Hai Li 提交于
In MDP5, CTL contains information of the whole pipeline whose output goes down to a display interface. In various cases, one interface may require 2 CRTCs, but only one CTL. Some interfaces also require to use certain CTLs. Instead of allocating CTL for each active CRTC, this change is to associate a CTL with each interface. Signed-off-by: NHai Li <hali@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 jilai wang 提交于
This change is to add properties alpha/zpos/blend_mode to mdp5 plane for alpha blending operation to generate the blended output. v1: Initial change v2: Change "premultilied" property to enum (Rob's comment) Signed-off-by: NJilai Wang <jilaiw@codeaurora.org> [Don't actually expose alpha/premultiplied props to userspace yet pending a chance for discussion and some userspace to exercise it] Signed-off-by: NRob Clark <robdclark@gmail.com>
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- 12 6月, 2015 1 次提交
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由 Hai Li 提交于
MDP FLUSH registers could indicate if the previous flush updates has taken effect at vsync boundary. Making use of this H/W feature can catch the vsync that happened between CRTC atomic_flush and *_wait_for_vblanks, to avoid unnecessary wait. This change allows kms CRTCs to use their own *_wait_for_commit_done functions to wait for FLUSH register cleared at vsync, before commit completion. Signed-off-by: NHai Li <hali@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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- 02 4月, 2015 2 次提交
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由 Stephane Viau 提交于
Some interfaces (WB, DSI Command Mode) need to be kicked off through a START Signal. This signal needs to be sent at the right time and requests in some cases to keep track of the pipeline status (eg: whether pipeline registers are flushed AND output WB buffers are ready, in case of WB interface). Signed-off-by: NStephane Viau <sviau@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Stephane Viau 提交于
DSI and WB interfaces need a more complex pipeline configuration than the current mdp5_ctl_set_intf(). For example, memory output connections need to be selected for WB. Interface mode (Video vs. Command modes) also need to be configured for DSI. This change takes care of configuring the whole pipeline as far as operation mode goes. DSI and WB interfaces will be added later. v2: rename macro to mdp5_cfg_intf_is_virtual() [pointed by Archit] Signed-off-by: NStephane Viau <sviau@codeaurora.org> [Remove temp bisectability hack -Rob] Signed-off-by: NRob Clark <robdclark@gmail.com>
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- 02 2月, 2015 1 次提交
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由 Stephane Viau 提交于
mdp5_ctl_set_intf()'s second argument should be "int", not "enum mdp5_intf". The passed in value is "intf", not "intf_id". Signed-off-by: NStephane Viau <sviau@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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- 21 11月, 2014 2 次提交
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由 Rob Clark 提交于
For example, use 'struct mdp5_smp *' everywhere instead of 'void *', but only declare it as 'struct mdp5_smp;' in common headers, so the struct body is still private. The accomplishes the desired modularity while still letting the compiler provide some type checking for us. Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Stephane Viau 提交于
MDP5 currently support one single CRTC with its private pipe. This change allows the configuration of multiple CRTCs with the possibility to attach several public planes to these CRTCs. Signed-off-by: NStephane Viau <sviau@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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