1. 24 4月, 2009 1 次提交
    • K
      davinci: major rework of clock, PLL, PSC infrastructure · c5b736d0
      Kevin Hilman 提交于
      This is a significant rework of the low-level clock, PLL and Power
      Sleep Controller (PSC) implementation for the DaVinci family.  The
      primary goal is to have better modeling if the hardware clocks and
      features with the aim of DVFS functionality.
      
      Highlights:
      - model PLLs and all PLL-derived clocks
      - model parent/child relationships of PLLs and clocks
      - convert to new clkdev layer
      - view clock frequency and refcount via /proc/davinci_clocks
      
      Special thanks to significant contributions and testing by David
      Brownell.
      
      Cc: David Brownell <dbrownell@users.sourceforge.net>
      Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
      c5b736d0
  2. 12 7月, 2007 1 次提交