1. 22 5月, 2015 4 次提交
    • V
      drm/i915: Remove the double register write from intel_disable_hdmi() · c52bcef7
      Ville Syrjälä 提交于
      IBX can have problems with the first write to the port register getting
      masked when enabling the port. We are trying to apply the workaround
      also when disabling the port where it's not needed, and we also try
      to apply it for CPT/PPT as well which don't need it. Just kill it.
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      [danvet: Resolve conflict with the remove CHV if block.]
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      c52bcef7
    • V
      drm/i915: Remove a bogus 12bpc "toggle" from intel_disable_hdmi() · ccbaefa0
      Ville Syrjälä 提交于
      The IBX 12bpc port enable toggle is only relevant when enabling
      the port, not when disabling it. Also this code doesn't actually
      toggle anything, and essentially just writes the port register
      one extra time. Furthermore CPT/PPT don't need such workarounds
      and yet we include them. Just kill it.
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      ccbaefa0
    • D
      drm/i915/skl: Deinit/init the display at suspend/resume · 5d96d8af
      Damien Lespiau 提交于
      We need to re-init the display hardware when going out of suspend. This
      includes:
      
        - Hooking the PCH to the reset logic
        - Restoring CDCDLK
        - Enabling the DDB power
      
      Among those, only the CDCDLK one is a bit tricky. There's some
      complexity in that:
      
        - DPLL0 (which is the source for CDCLK) has two VCOs, each with a set
          of supported frequencies. As eDP also uses DPLL0 for its link rate,
          once DPLL0 is on, we restrict the possible eDP link rates the chosen
          VCO.
        - CDCLK also limits the bandwidth available to push pixels.
      
      So, as a first step, this commit restore what the BIOS set, until I can
      do more testing.
      
      In case that's of interest for the reviewer, I've unit tested the
      function that derives the decimal frequency field:
      
        #include <stdio.h>
        #include <stdint.h>
        #include <assert.h>
      
        #define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x)))
      
        static const struct dpll_freq {
                unsigned int freq;
                unsigned int decimal;
        } freqs[] = {
                { .freq = 308570, .decimal = 0b01001100111},
                { .freq = 337500, .decimal = 0b01010100001},
                { .freq = 432000, .decimal = 0b01101011110},
                { .freq = 450000, .decimal = 0b01110000010},
                { .freq = 540000, .decimal = 0b10000110110},
                { .freq = 617140, .decimal = 0b10011010000},
                { .freq = 675000, .decimal = 0b10101000100},
        };
      
        static void intbits(unsigned int v)
        {
                int i;
      
                for(i = 10; i >= 0; i--)
                        putchar('0' + ((v >> i) & 1));
        }
      
        static unsigned int freq_decimal(unsigned int freq /* in kHz */)
        {
                return (freq - 1000) / 500;
        }
      
        static void test_freq(const struct dpll_freq *entry)
        {
                unsigned int decimal = freq_decimal(entry->freq);
      
                printf("freq: %d, expected: ", entry->freq);
                intbits(entry->decimal);
                printf(", got: ");
                intbits(decimal);
                putchar('\n');
      
                assert(decimal == entry->decimal);
        }
      
        int main(int argc, char **argv)
        {
                int i;
      
                for (i = 0; i < ARRAY_SIZE(freqs); i++)
                        test_freq(&freqs[i]);
      
                return 0;
        }
      
      v2:
        - Rebase on top of -nightly
        - Use (freq - 1000) / 500 for the decimal frequency (Ville)
        - Fix setting the enable bit of HSW_NDE_RSTWRN_OPT (Ville)
        - Rename skl_display_{resume,suspend} to skl_{init,uninit}_cdclk to
          be consistent with the BXT code (Ville)
        - Store boot CDCLK in ddi_pll_init (Ville)
        - Merge dev_priv's skl_boot_cdclk into cdclk_freq
        - Use LCPLL_PLL_LOCK instead of (1 << 30) (Ville)
        - Replace various '0' by SKL_DPLL0 to be a bit more explicit that
          we're programming DPLL0
        - Busy poll the PCU before doing the frequency change. It takes about
          3/4 cycles, each separated by 10us, to get the ACK from the CPU
          (Ville)
      
      v3:
        - Restore dev_priv->skl_boot_cdclk, leaving unification with
          dev_priv->cdclk_freq for a later patch (Daniel, Ville)
      Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      5d96d8af
    • C
      drm/i915: Free RPS boosts for all laggards · e61b9958
      Chris Wilson 提交于
      If the client stalls on a congested request, chosen to be 20ms old to
      match throttling, allow the client a free RPS boost.
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      [danvet: s/rq/req/]
      [danvet: s/0/NULL/ reported by 0-day build]
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      e61b9958
  2. 21 5月, 2015 10 次提交
  3. 20 5月, 2015 26 次提交