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  1. 25 4月, 2012 1 次提交
  3. 10 3月, 2012 4 次提交
  5. 08 3月, 2012 1 次提交
  7. 03 3月, 2012 1 次提交
    • K
      ARM: S3C24XX: change the ARCH_S3C2410 to ARCH_S3C24XX · b130d5c2
      由 Kukjin Kim 提交于 
      This patch changes the ARCH name to "ARCH_S3C24XX" for Samsung
S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443,
and S3C2450 SoCs so that we can merge the mach-xxx directories
and plat-s3c24xx dir. to just one mach-s3c24xx for them.

I think this should be sent to upstream via samsung tree because
this touches many samsung stuff.

Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: Richard Purdie <rpurdie@rpsys.net>
Cc: Chris Ball <cjb@laptop.org>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Greg Kroah-Hartman <gregkh@suse.de>
[for the gadget part:]
Acked-by: NFelipe Balbi <balbi@ti.com>
[for the framebuffer (video) part:]
Acked-by: NFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>
[For the watchdog-part:]
Acked-by: NWim Van Sebroeck <wim@iguana.be>
Cc: Sangbeom Kim <sbkim73@samsung.com>
Cc: Liam Girdwood <lrg@ti.com>
Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
      b130d5c2
  9. 06 2月, 2012 1 次提交
  11. 02 1月, 2012 1 次提交
  13. 08 12月, 2011 2 次提交
  15. 14 11月, 2011 1 次提交
  17. 29 10月, 2011 1 次提交
  19. 25 10月, 2011 1 次提交
  21. 15 7月, 2011 2 次提交
    • S
      spi/imx: use soc name in spi device type naming scheme · 04ee5854
      由 Shawn Guo 提交于 
      Software defined version number is not stable enough to be used
in device type naming scheme.  The patch changes it to use implicit
soc name for spi device type definition.  In this way, we can easily
align the naming scheme with device tree binding, which comes later.

It removes fifosize from spi_imx_data and adds devtype there, so that
fifosize can be set in an inline function according to devtype.
Also, cpu_is_mx can be replaced by inline functions checking devtype.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
      04ee5854
    • S
      spi/imx: merge type SPI_IMX_VER_0_7 into SPI_IMX_VER_0_4 · 2a64a90a
      由 Shawn Guo 提交于 
      The only difference between SPI_IMX_VER_0_7 and SPI_IMX_VER_0_4 is
.config function.  The patch uses cpu_is_mx35 (to be removed) as the
temporary solution to consolidate functions spi_imx0_4_config and
spi_imx0_7_config into mx31_config.  As a result, type SPI_IMX_VER_0_7
can be merged into SPI_IMX_VER_0_4.

It also renames function spi_imx0_4_reset to mx31_reset to keep
consistency with other function naming.

A couple of redundant macros, MX3_CSPISTAT and MX3_CSPISTAT_RR,
together with the useless type SPI_IMX_VER_0_5 also get cleaned up.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
      2a64a90a
  23. 05 7月, 2011 1 次提交
  25. 09 6月, 2011 1 次提交
  27. 06 6月, 2011 1 次提交
  29. 27 5月, 2011 1 次提交
  31. 20 5月, 2011 1 次提交
  33. 15 3月, 2011 1 次提交
  35. 08 3月, 2011 3 次提交
  37. 23 2月, 2011 3 次提交
  39. 19 1月, 2011 1 次提交
  41. 14 1月, 2011 1 次提交
  43. 13 1月, 2011 1 次提交
  45. 24 12月, 2010 1 次提交
  47. 01 12月, 2010 1 次提交
  49. 18 11月, 2010 1 次提交
  51. 10 11月, 2010 2 次提交
  53. 22 10月, 2010 1 次提交
    • E
      spi: add spi_tegra driver · 0c03a1dd
      由 Erik Gilling 提交于 
      v2 changes:
  from Thierry Reding:
    * add "select TEGRA_SYSTEM_DMA" to Kconfig
  from Grant Likely:
    * add oneline description to header
    * inline references to DRIVER_NAME
    * inline references to BUSY_TIMEOUT
    * open coded bytes_per_word()
    * spi_readl/writel -> spi_tegra_readl/writel
    * move transfer validation to spi_tegra_transfer
    * don't request_mem_region iomem as platform bus does that for us
    * __exit -> __devexit

v3 changes:
  from Russell King:
    * put request_mem_region back int
  from Grant Likely:
    * remove #undef DEBUG
    * add SLINK_ to register bit defines
    * remove unused bytes_per_word
    * make spi_tegra_readl/writel static linine
    * various refactoring for clarity
    * mark err if BSY bit is not cleared after 1000 retries
    * move spinlock to protect setting of RDY bit
    * subsys_initcall -> module_init

v3 changes:
  from Grant Likely:
    * update spi_tegra to use PTR_ERRless dma API

v4 changes:
  from Grant Likely:
    * remove empty spi_tegra_cleanup fucntion
    * allow device ids of -1
Signed-off-by: NErik Gilling <konkers@android.com>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Cc: Thierry Reding <thierry.reding@avionic-design.de>
Cc: Russell King <linux@arm.linux.org.uk>

spi: tegra: cleanups from upstream review

Change-Id: Icecf7e64efcb39de072a15234ba1faa4bad40d25
Signed-off-by: NErik Gilling <konkers@android.com>
      0c03a1dd
  55. 13 10月, 2010 3 次提交
    • M
      spi/fsl_spi: add eSPI controller support · 8b60d6c2
      由 Mingkai Hu 提交于 
      Add eSPI controller support based on the library code spi_fsl_lib.c.

The eSPI controller is newer controller 85xx/Pxxx devices supported.
There're some differences comparing to the SPI controller:

1. Has different register map and different bit definition
   So leave the code operated the register to the driver code, not
   the common code.

2. Support 4 dedicated chip selects
   The software can't controll the chip selects directly, The SPCOM[CS]
   field is used to select which chip selects is used, and the
   SPCOM[TRANLEN] field is set to tell the controller how long the CS
   signal need to be asserted. So the driver doesn't need the chipselect
   related function when transfering data, just set corresponding register
   fields to controll the chipseclect.

3. Different Transmit/Receive FIFO access register behavior
   For SPI controller, the Tx/Rx FIFO access register can hold only
   one character regardless of the character length, but for eSPI
   controller, the register can hold 4 or 2 characters according to
   the character lengths. Access the Tx/Rx FIFO access register of the
   eSPI controller will shift out/in 4/2 characters one time. For SPI
   subsystem, the command and data are put into different transfers, so
   we need to combine all the transfers to one transfer in order to pass
   the transfer to eSPI controller.

4. The max transaction length limitation
   The max transaction length one time is limitted by the SPCOM[TRANSLEN]
   field which is 0xFFFF. When used mkfs.ext2 command to create ext2
   filesystem on the flash, the read length will exceed the max value of
   the SPCOM[TRANSLEN] field.
Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
      8b60d6c2
    • M
      spi/mpc8xxx: refactor the common code for SPI/eSPI controller · b36ece83
      由 Mingkai Hu 提交于 
      Refactor the common code in file spi_fsl_spi.c to spi_fsl_lib.c used
by SPI/eSPI controller driver as a library, and leave the QE/CPM SPI
controller code in the SPI controller driver spi_fsl_spi.c.

Because the register map of the SPI controller and eSPI controller
is so different, also leave the code operated the register to the
driver code, not the common code.
Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
      b36ece83
    • M
      spi/mpc8xxx: rename spi_mpc8xxx.c to spi_fsl_spi.c · 3272029f
      由 Mingkai Hu 提交于 
      This will pave the way to refactor out the common code which can be used
by the eSPI controller driver, and rename the SPI controller dirver to the
file spi_fsl_spi.c.
Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
      3272029f