1. 11 8月, 2017 6 次提交
    • J
    • J
      Documentation/i915: remove sphinx conversion artefact · 83e92c21
      Jani Nikula 提交于
      Remove old warning about docproc directive that's not supported in the
      Sphinx toolchain.
      Signed-off-by: NJani Nikula <jani.nikula@intel.com>
      Reviewed-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/7fc8a110b78a9dc9a585dce643b68b4200b7e793.1502368010.git.jani.nikula@intel.com
      83e92c21
    • B
      drm/i915: Add format modifiers for Intel · 714244e2
      Ben Widawsky 提交于
      This was based on a patch originally by Kristian. It has been modified
      pretty heavily to use the new callbacks from the previous patch.
      
      v2:
        - Add LINEAR and Yf modifiers to list (Ville)
        - Combine i8xx and i965 into one list of formats (Ville)
        - Allow 1010102 formats for Y/Yf tiled (Ville)
      
      v3:
        - Handle cursor formats (Ville)
        - Put handling for LINEAR in the mod_support functions (Ville)
      
      v4:
        - List each modifier explicitly in supported modifiers (Ville)
        - Handle the CURSOR plane (Ville)
      
      v5:
        - Split out cursor and sprite handling (Ville)
      
      v6:
        - Actually use the sprite funcs (Emil)
        - Use unreachable (Emil)
      
      v7:
        - Only allow Intel modifiers and LINEAR (Ben)
      
      v8
        - Fix spite assert introduced in v6 (Daniel)
      
      v9
        - Change vendor check logic to avoid magic 56 (Emil)
        - Reorder skl_mod_support (Ville)
        - make intel_plane_funcs static, could be done as of v5 (Ville)
        - rename local variable intel_format_modifiers to modifiers (Ville)
          - actually use sprite modifiers
        - split out modifier/formats by platform (Ville)
      
      v10:
        - Undo vendor check from v9
      
      v11:
        - Squash CCS advertisement into this patch (daniels)
        - Don't advertise CCS on higher sprite planes (daniels)
      
      v12:
        - Don't advertise Y-tiled or CCS on any sprite planes, since we don't
          allocate enough DDB space for it to work. (daniels)
      
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> (v8)
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: NDaniel Stone <daniels@collabora.com>
      714244e2
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      drm/i915: Add render decompression support · 2e2adb05
      Ville Syrjälä 提交于
      SKL+ display engine can scan out certain kinds of compressed surfaces
      produced by the render engine. This involved telling the display engine
      the location of the color control surfae (CCS) which describes
      which parts of the main surface are compressed and which are not. The
      location of CCS is provided by userspace as just another plane with its
      own offset.
      
      Add the required stuff to validate the user provided AUX plane metadata
      and convert the user provided linear offset into something the hardware
      can consume.
      
      Due to hardware limitations we require that the main surface and
      the AUX surface (CCS) be part of the same bo. The hardware also
      makes life hard by not allowing you to provide separate x/y offsets
      for the main and AUX surfaces (excpet with NV12), so finding suitable
      offsets for both requires a bit of work. Assuming we still want keep
      playing tricks with the offsets. I've just gone with a dumb "search
      backward for suitable offsets" approach, which is far from optimal,
      but it works.
      
      Also not all planes will be capable of scanning out compressed surfaces,
      and eg. 90/270 degree rotation is not supported in combination with
      decompression either.
      
      This patch may contain work from at least the following people:
      * Vandana Kannan <vandana.kannan@intel.com>
      * Daniel Vetter <daniel@ffwll.ch>
      * Ben Widawsky <ben@bwidawsk.net>
      
      v2: Deal with display workarounds 0390, 0531, 1125 (Paulo)
      v3: Pretend CCS tiles are regular 128 byte wide Y tiles (Jason)
          Put the AUX register defines to the correct place
          Fix up the slightly bogus rotation check
      v4: Use I915_WRITE_FW() due to plane update locking changes
          s/return -EINVAL/goto err/ in intel_framebuffer_init()
          Eliminate a bunch hardcoded numbers in CCS code
      
      v5: (By Ben)
      conflict resolution +
      -               res_blocks += fixed_16_16_to_u32_round_up(y_tile_minimum);
      +               res_blocks += fixed16_to_u32_round_up(y_tile_minimum);
      
      v6: (daniels) Fix botched commit message.
      
      Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
      Cc: Daniel Vetter <daniel@ffwll.ch>
      Cc: Ben Widawsky <ben@bwidawsk.net>
      Cc: Jason Ekstrand <jason@jlekstrand.net>
      Signed-off-by: NVille Syrjä <ville.syrjala@linux.intel.com>
      Reviewed-by: Ben Widawsky <ben@bwidawsk.net> (v1)
      Reviewed-by: NDaniel Stone <daniels@collabora.com>
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: NDaniel Stone <daniels@collabora.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/20170801165817.7063-1-ben@bwidawsk.net
      2e2adb05
    • V
      drm/i915: Implement .get_format_info() hook for CCS · bbfb6ce8
      Ville Syrjälä 提交于
      SKL+ display engine can scan out certain kinds of compressed surfaces
      produced by the render engine. This involved telling the display engine
      the location of the color control surfae (CCS) which describes which
      parts of the main surface are compressed and which are not. The location
      of CCS is provided by userspace as just another plane with its own offset.
      
      By providing our own format information for the CCS formats, we should
      be able to make framebuffer_check() do the right thing for the CCS
      surface as well.
      
      Note that we'll return the same format info for both Y and Yf tiled
      format as that's what happens with the non-CCS Y vs. Yf as well. If
      desired, we could potentially return a unique pointer for each
      pixel_format+tiling+ccs combination, in which case we immediately be
      able to tell if any of that stuff changed by just comparing the
      pointers. But that does sound a bit wasteful space wise.
      
      v2: Drop the 'dev' argument from the hook
      v3: Include the description of the CCS surface layout
      v4: Pretend CCS tiles are regular 128 byte wide Y tiles (Jason)
      v5: Re-drop 'dev', fix commit message, add missing drm_fourcc.h
          description of CCS layout. (daniels)
      
      Cc: Daniel Vetter <daniel@ffwll.ch>
      Cc: Ben Widawsky <ben@bwidawsk.net>
      Cc: Jason Ekstrand <jason@jlekstrand.net>
      Acked-by: NJason Ekstrand <jason@jlekstrand.net>
      Reviewed-by: Ben Widawsky <ben@bwidawsk.net> (v3)
      Reviewed-by: NDaniel Stone <daniels@collabora.com>
      Signed-off-by: NVille Syrjä <ville.syrjala@linux.intel.com>
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: NDaniel Stone <daniels@collabora.com>
      bbfb6ce8
    • D
      Merge airlied/drm-next into drm-intel-next-queued · 148b1e11
      Daniel Vetter 提交于
      Ben Widawsky/Daniel Stone need the extended modifier support from
      drm-misc to be able to merge CCS support for i915.ko
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      148b1e11
  2. 10 8月, 2017 3 次提交
    • C
      drm/i915: Supply the engine-id for our mock_engine() · 3ec0af7f
      Chris Wilson 提交于
      In the original selftest, we didn't care what the engine->id was, just
      that it could uniquely identify it. Later though, we started tracking
      the mock engines in the fixed size arrays around the drm_i915_private and
      so we now require their indices to be correct. This becomes an issue when
      using the standalone harness which runs all available tests at module load,
      and so we quickly assign an out-of-bounds index to an engine as we
      reallocate the mock GEM device between tests. It doesn't show up in
      igt/drv_selftest as that runs each subtest individually.
      
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102045Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Link: https://patchwork.freedesktop.org/patch/msgid/20170809163930.26470-1-chris@chris-wilson.co.ukReviewed-by: NMika Kuoppala <mika.kuoppala@intel.com>
      3ec0af7f
    • D
      Merge tag 'drm-misc-next-2017-08-08' of git://anongit.freedesktop.org/git/drm-misc into drm-next · 09ef2378
      Dave Airlie 提交于
      UAPI Changes:
      - vc4: Add ioctl to allow attaching a label to a bo (Eric)
      - Add new format/modifier blob plane property (Ben)
      - armada: Use __u32/__u64 instead of uint32_t/uint64_t (Mikko)
      - [kinda uapi] fb_helper: Expose display_info size via fb_info (David)
      
      Core Changes:
      - Default gem_dumb_[map_offset|destroy] as mmap/destroy implementations (Noralf)
      - Simplify atomic properties by removing the helpers and handling in core (Daniel)
      
      Driver Changes:
      - stm: Add STM32 DSI controller driver (Phillipe)
      - vc4: Add HDMI CEC support (Hans)
      - rockchip: Refactor register init & soc version handling (Mark)
      - misc: Remove .load_lut, .gamma_set, .gamma_get dead code (Peter)
      - dw-hdmi: Add HDMI CEC support (Russell)
      
      Cc: Philippe CORNU <philippe.cornu@st.com>
      Cc: Hans Verkuil <hans.verkuil@cisco.com>
      Cc: Eric Anholt <eric@anholt.net>
      Cc: Noralf Trønnes <noralf@tronnes.org>
      Cc: Ben Widawsky <ben@bwidawsk.net>
      Cc: Mark yao <mark.yao@rock-chips.com>
      Cc: Peter Rosin <peda@axentia.se>
      Cc: Russell King <rmk+kernel@armlinux.org.uk>
      Cc: Mikko Rapeli <mikko.rapeli@iki.fi>
      Cc: David Lechner <david@lechnology.com>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      
      * tag 'drm-misc-next-2017-08-08' of git://anongit.freedesktop.org/git/drm-misc: (107 commits)
        drm: Nuke drm_atomic_legacy_backoff
        drm: Nuke drm_atomic_helper_connector_dpms
        drm: Nuke drm_atomic_helper_connector_set_property
        drm: Nuke drm_atomic_helper_plane_set_property
        drm: Nuke drm_atomic_helper_crtc_set_property
        drm: Handle properties in the core for atomic drivers
        drm: Don't update property values for atomic drivers
        drm/omap: Rework the rotation-on-crtc hack
        drm/radeon: Use the drm_driver.dumb_destroy default
        drm/i915: Use the drm_driver.dumb_destroy default
        drm/sti: Use .dumb_map_offset and .dumb_destroy defaults
        drm: bridge: synopsys/dw-hdmi: Provide default configuration function for HDMI 2.0 PHY
        drm/fb-helper: pass physical dimensions to fbdev
        uapi drm/armada_drm.h: use __u32 and __u64 instead of uint32_t and uint64_t
        drm/bridge: dw-hdmi: remove CEC engine register definitions
        drm/bridge: dw-hdmi: add cec driver
        drm/bridge: dw-hdmi: add missing cec_notifier_put
        drm: remove unused and redundant callbacks
        staging: vboxvideo: remove dead gamma lut code
        drm: dw-hdmi-i2s: add missing company name on Copyright
        ...
      09ef2378
    • J
      drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init · 912d6412
      Jim Bride 提交于
      Bit 29 of SRD_CTL needs to have its value preserved according to the
      B-Spec, so right before we write out the register we go ahead and read
      the register and preserve the value of that bit before we write out
      the configured register value.
      
      v2: Spaces => tabs, minor name change, and commit message wording (Rodrigo)
      
      Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Jani Nikula <jani.nikula@intel.com>
      Signed-off-by: NJim Bride <jim.bride@linux.intel.com>
      Reviewed-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
      Signed-off-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/1502229094-13392-1-git-send-email-jim.bride@linux.intel.com
      912d6412
  3. 09 8月, 2017 1 次提交
  4. 08 8月, 2017 14 次提交
  5. 07 8月, 2017 8 次提交
  6. 05 8月, 2017 1 次提交
  7. 04 8月, 2017 7 次提交