The pllp_out2 should be integer only, the fractional bit should always be 0.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The pllc and pllxc code weren't always using the correct pdiv_map to
map between the post divider value and the hw p field. This could result
in illegal values being programmed in the hw.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

If the current rate of parent clock is sufficient to provide child a
requested rate with a proper divider setting, the rate change request
should not be propagated.  Instead, changing the divider setting is good
enough to get child clock run at the requested rate.

On an imx6q clock configuration illustrated below,

  ahb --> ipg --> ipg_per
  132M    66M     66M

calling clk_set_rate(ipg_per, 22M) with the current
clk_divider_bestdiv() implementation will result in the rate change up
to ahb level like the following, because of the unnecessary/incorrect
rate change propagation.

  ahb --> ipg --> ipg_per
  66M     22M     22M

Fix the problem by trying to see if the requested rate can be achieved
by simply changing the divider value, and in that case return the
divider immediately from function clk_divider_bestdiv() as the best
one, so that all those unnecessary rate change propagation can be saved.
Reported-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

First clocks definition version of PRCMU and PRCC clocks for u8540 platform
Signed-off-by: NPhilippe Begnic <philippe.begnic@st.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Align on u8500 version, pass clock base address in clk_init functions
for u8540 and u9540.
Signed-off-by: NLinus Walleij <linus.walleij@stericsson.com>
Signed-off-by: NPhilippe Begnic <philippe.begnic@st.com>
Reviewed-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The msenc clock's register was set to the usb3 clock's register.
Signed-off-by: NMikko Perttunen <mperttunen@nvidia.com>
Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Use common of_clk_init() function for clocks initialization.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: NThierry Reding <thierry.reding@gmail.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Tegra has a blink timer register that allows to modulate the
clk_32k clock before outputting it. Since clk_32k is presented to the
kernel as a fixed clock, make sure this register does not tamper with
the clock frequency and that clk_32k is outputted as-is, similarly to
what is done on t20 and t30.
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Number of parents for clk_out_2 and clk_out_3 was incorrectly set
to clk_out1_parents. Even though it did not break anything since the
size was same better to fix.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: NThierry Reding <thierry.reding@gmail.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch adds a basic clock driver for the TI-Nspire calculator
series.

Changes from v1:
* Removed filename in header comment
* Removed unnecessary #undef EXTRACT statement
Signed-off-by: NDaniel Tang <dt.tangr@gmail.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: fixed $SUBJECT and changelog max width]

Use the wrapper functions for getting and setting the driver data using
platform_device instead of using dev_{get,set}_drvdata() with &pdev->dev,
so we can directly pass a struct platform_device.
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The compatible string of clock is changed from *-2 to *-2.0
on chassis 2. So updated it accordingly.
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: improved $SUBJECT line]

In some architectures, the #define cpu_data is not a "macro-function",
so the compiler will substitute the identifier with probably something
wrong.
Signed-off-by: NGiacomo A. Catenazzi <cate@cateee.net>
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
[emilio@elopez.com.ar: use cpu_mux_data instead of this_cpu_data]
Signed-off-by: NMike Turquette <mturquette@linaro.org>

'mout_mpll' is added the list of parent clocks for 'mout_cpu'.
'mout_mpll' is an alias to the clock 'sclk_mpll'. Hence 'sclk_mpll'
should be added to the list of parent clocks.

This results in an error when cpufreq driver for EXYNOS5250 tries to
set 'mout_mpll' as a parent for 'mout_cpu'.

clk_set_parent: clk sclk_mpll can not be parent of clk mout_cpu
Signed-off-by: NTushar Behera <tushar.behera@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

cpufreq driver for EXYNOS5250 is not a platform driver, hence we cannot
currently pass the clock names through a device tree node. Instead, we
need to make them available through a global alias.

cpufreq driver for EXYNOS5250 requires four clocks - 'armclk',
'mout_cpu', 'mout_mpll' and 'mout_apll'.

'armclk' has already been defined with an alias, 'mout_cpu', 'mout_mpll'
and 'mout_apll' are now defined with an alias.
Signed-off-by: NTushar Behera <tushar.behera@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The divisor adjustment code to ensure that a divisor is not rounded down,
thereby giving a rate higher than requested, is unnecessary and in some
instances results in the actual rate being much lower than requested due to
rounding errors.

The test is already performed in vtwm_dclk_round_rate(), which is always
called when clk_set_rate is called. Due to rounding errors in the line:
divisor = parent_rate / rate (clk-vt8500.c:160) we will sometimes end up
adjusting the divisor twice - first in round_rate and then again in set_rate.

This patch removes the test/adjustment in vtwm_dclk_set_rate.
Signed-off-by: NTony Prisk <linux@prisktech.co.nz>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The WM8850 has a different PLL clock to the previous versions. This
patch adds support for the WM8850-style PLL clocks.
Signed-off-by: NTony Prisk <linux@prisktech.co.nz>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

With deferred probing, late_initcall() is too soon to declare a clock as
unused. Wait for deferred probing to finish before declaring a clock as
unused. Since deferred probing is done in late_initcall(), do the unused
check to late_initcall_sync.
Signed-off-by: NSaravana Kannan <skannan@codeaurora.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Current code looks strange because calling wm831x_clkout_set_parent() with 0 as
parent parameter, wm831x_clkout_get_parent() will return 1.

According to the datasheet:
R16528 (4090h) Clock Control1
        BIT 0: CLKOUT output source select
                0 = FLL output
                1 = 32.768kHz oscillator

Thus fix the entry order in wm831x_clkout_parents[] to make it has
the same meaning as the datasheet and make the return value
of wm831x_clkout_get_parent() consistent with the parent pass to
wm831x_clkout_set_parent().
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

According to the datasheet, FLL Enable is controlled by
R16530 (4092h) FLL Control1
        BIT 0: FLL Enable
                0 = Disable
                1 = Enable

Thus the code should update WM831X_FLL_CONTROL_1 register rather than
WM831X_FLL_CONTROL_2 register.

Also fixes a trivial typo in dev_crit message.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

With of_clk_provider stubs for CONFIG_OF not set, we can now also enable
clk-si5351 on those architectures.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Without this patch, the following race condition is possible.
* clk-A has two parents - clk-X and clk-Y.
* All three are disabled and clk-X is current parent.
* Thread A: clk_set_parent(clk-A, clk-Y).
* Thread A: <snip execution flow>
* Thread A: Grabs enable lock.
* Thread A: Sees enable count of clk-A is 0, so doesn't enable clk-Y.
* Thread A: Updates clk-A SW parent to clk-Y
* Thread A: Releases enable lock.
* Thread B: clk_enable(clk-A).
* Thread B: clk_enable() enables clk-Y, then enabled clk-A and returns.

clk-A is now enabled in software, but not clocking in hardware since the
hardware parent is still clk-X.

The only way to avoid race conditions between clk_set_parent() and
clk_enable/disable() is to ensure that clk_enable/disable() calls don't
require changes to hardware enable state between changes to software clock
topology and hardware clock topology.

The options to achieve the above are:
1. Grab the enable lock before changing software/hardware topology and
   release it afterwards.
2. Keep the clock enabled for the duration of software/hardware topology
   change so that any additional enable/disable calls don't try to change
   the hardware state. Once the topology change is complete, the clock can
   be put back in its original enable state.

Option (1) is not an acceptable solution since the set_parent() ops might
need to sleep.

Therefore, this patch implements option (2).

This patch doesn't violate any API semantics. clk_disable() doesn't
guarantee that the clock is actually disabled. So, no clients of a clock
can assume that a clock is disabled after their last call to clk_disable().
So, enabling the clock during a parent change is not a violation of any API
semantics.

This also has the nice side effect of simplifying the error handling code.
Signed-off-by: NSaravana Kannan <skannan@codeaurora.org>
Acked-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: fixed up whitespace issue]

When the si5351 driver is a kernel module, it is loaded into memory
from its i2c device IDs, but not from its DT compatible properties.

This patch declares the i2c device IDs of all chip variants.
Signed-off-by: NJean-Francois Moine <moinejf@free.fr>
Acked-by: NJason Cooper <jason@lakedaemon.net>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The A13 has a lot less clocks than the one found in the Allwinner A10.
Add these stripped down clocks to the clock driver and in the
documentation.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NEmilio López <emilio@elopez.com.ar>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Change soc-audio related clk_register_clkdev() device names to reflect
the ones actually used in current snd-soc-mop500 and ab8500-codec
drivers.

Cc: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NFabio Baltieri <fabio.baltieri@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch adds platform data and DT bindings to allow to overwrite
the stored disabled state for each clock output.
Signed-off-by: NMarek Belisko <marek.belisko@streamunlimited.com>
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This adds the clock driver for Freescale PowerPC corenet
series SoCs using common clock infrastructure.
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: NLi Yang <leoli@freescale.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

AC97 controller clock is hardwired to pll_a_out0.
Signed-off-by: NLucas Stach <dev@lynxeye.de>
Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Tested-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The USB clocks are just clock gates, so no need to set a specific clock.
In fact trying to set a specific clock is just a NOP if the requested
clockrate is the same as those of the parent (clk_m) or will trigger a
WARN_ON() if rates don't match up.

As we are not setting a specific rate, nor activating the clocks at
init, there is no point in keeping the the usb entries in the clock init
table.
Signed-off-by: NLucas Stach <dev@lynxeye.de>
Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Tested-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The DMA controller in Lynxpoint is enumerated as a regular ACPI device now. To
work properly it is using the LPSS root clock as a functional clock. That's why
we have to register the clock device accordingly to the ACPI ID of the DMA
controller. The acpi_lpss.c module is responsible to do the job.

This patch also removes hardcoded name of the DMA device in clk-lpt.c and the
name of the root clock in acpi_lpss.c.
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

This is primarily useful when there's a driver that doesn't claim clocks
properly, but the bootloader leaves them on. It's not expected to be used
in normal cases, but for bringup and debug it's very useful to have the
option to not gate unclaimed clocks that are still on.
Signed-off-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: fixed up trivial merge issue]

commit 688f7d8c ("clk: exynos5250: Fix divider values for
sclk_mmc{0,1,2,3}") incorrectly sets the divider for sclk_mmc{0,1,2,3}
to fix the wrong clock value. Though this fixed issue with Arndale,
it created regressions for other boards like Snow.

On Exynos5250, sclk_mmc<n> is generated like below (as per the clock
names in drivers/clk/samsung/clk-exynos5250.c)

mout_group1_p ==> mout_mmc<n> ==>
		div_mmc<n> ==> div_mmc_pre<n> => sclk_mmc<n>

Earlier div_mmc<n> was set as the parent for sclk_mmc<n>, hence
div_mmc_pre<n> was not getting referred in kernel code and depending
on its value set during preboot, sclk_mmc<n> value was different for
various boards.

Setting the correct clock generation path should fix the issues
reported in above referenced commit. The changes committed during the
earlier patch has also been reverted here.
Reported-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NTushar Behera <tushar.behera@linaro.org>
Tested-by: NDoug Anderson <dianders@chromium.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

As reported by Rob Herring[1] there were some mismatched types between
drivers/clk/ux500/clk.h and the corresponding function definitions:

drivers/clk/ux500/clk-prcc.c:145:13: error: conflicting types for 'clk_reg_prcc_pclk'
drivers/clk/ux500/clk-prcc.c:155:13: error: conflicting types for 'clk_reg_prcc_kclk'

[1] http://article.gmane.org/gmane.linux.ports.arm.kernel/232246Signed-off-by: NMike Turquette <mturquette@linaro.org>
Cc: Rob Herring <robherring2@gmail.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>

The new common clock drivers for exynos are using compile
time constants and soc_is_exynos* macros to provide backwards
compatibility for pre-DT systems, which is not possible with
multiplatform kernels. This moves all the necessary
information back into platform code and removes the mach/*
header inclusions.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Cc: Mike Turquette <mturquette@linaro.org>

Factor out the SP810 clocking code into a separate driver,
selecting better (faster) parent at clk_prepare() time.
This is to avoid problems with clocking infrastructure
initialisation order, in particular to avoid dependency
of fixed clock being initialized before SP810. It also
makes vexpress platform OF-based clock initialisation code
unnecessary.
Signed-off-by: NPawel Moll <pawel.moll@arm.com>
Tested-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: add .unprepare, FIXME comment, cleaned up code]

Calling clk-si5351 driver non-OF ready was too early. This patch
makes clk-si5351 depend on CONFIG_OF again, until things get sorted out.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reported-by: NStephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: fixed spelling of Stephen's name]

The common clock api provides some helpers for clk-providers but does
not export these helpers. This hinders clk-providers to be built as modules.
This patch adds __clk_get_flags() to the list of exported symbols.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

With this patch, the socfpga clk driver is able to query the clock and clock
rates appropriately.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Reviewed-by: NPavel Machek <pavel@denx.de>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The case of PLL_TYPE_WM8750 in both these functions is missing a break
statement causing a fall-through to the default: case.

Insert the missing break statements.
Signed-off-by: NTony Prisk <linux@prisktech.co.nz>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This commit uses the new fixed-rate support on the composite clock to
unify osc24M_fixed and osc24M clocks, so it matches the actual hardware.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: replace clk_register_gatable_osc with a call to
clk_register_composite]