1. 08 7月, 2008 19 次提交
    • C
      x86: nmi_watchdog - use NMI_NONE by default · c376d454
      Cyrill Gorcunov 提交于
      There is no need to keep NMI_DISABLED definition and use it
      for nmi_watchdog by default. Here is the point why:
      
      - IO-APIC and APIC chips are programmed for nmi_watchdog support at very
        early stage of kernel booting and not having nmi_watchdog specified as
        boot option lead only to nmi_watchdog becomes to NMI_NONE anyway
      - enable nmi_watchdog thru /proc/sys/kernel/nmi if it was not specified at
        boot is not possible too (even having this sysfs entry)
      Signed-off-by: NCyrill Gorcunov <gorcunov@gmail.com>
      Cc: macro@linux-mips.org
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      c376d454
    • G
      x86: change __setup_vector_irq with setup_vector_irq · 3fde6900
      Glauber Costa 提交于
      We create a version of it for i386, and then take the CONFIG_X86_64
      ifdef out of the game. We could create a __setup_vector_irq for i386,
      but it would incur in an unnecessary lock taking. Moreover, it is better
      practice to only export setup_vector_irq anyway.
      Signed-off-by: NGlauber Costa <gcosta@redhat.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      3fde6900
    • M
      x86: fix IO APIC breakage on HP nx6325, v2 · 7f0dbbc0
      Maciej W. Rozycki 提交于
      > That helped a lot, the system seems to work normally now.
      >
      > Here's the relevant snippet from dmesg:
      >
      > [    0.108006] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
      > [    0.108006] ..MP-BIOS bug: 8254 timer not connected to IO-APIC
      > [    0.108006] ...trying to set up timer (IRQ0) through the 8259A ... <3>
      > [    0.108006] ..... (found apic 0 pin 2) ...<3> failed.
      > [    0.108006] ...trying to set up timer as Virtual Wire IRQ...<3> works.
      >
      > and the whole thing is at: http://www.sisk.pl/kernel/debug/20080618/dmesg-2.log
      
       Hmm, that only proved the 8259A is indeed wired to the pin #2 of the I/O
      APIC.
      
      > I, personally, don't have any and AMD only has SB600 documentation on its
      > web page (it's still marked as "AMD confidential" ;-)).
      
       Well, the IC block is most likely the same as that's not rocket science
      and once done there is no need to fiddle with that.  That written, I am
      afraid there is nothing useful about the IC in the document, except that
      it's there and consists of an I/O APIC providing 24 inputs and the usual
      pair of 8259A cores.  Thanks for the reference anyway.
      
      > There is an interrupt controller in there, but I'm not sure if there's any
      > 8259A.  The northbridge is on the CPU, actually.
      
       I will praise the day someone ships an x86 machine without an 8259A core!
      
       As expressed in another mail I suspect there may actually be a direct
      route from the 8254 to INTIN0 in the southbridge -- this is what other
      bootstrap logs seen in the Internet suggest.  This would mean this
      particular BIOS is buggy (is it the latest version?) and provides an
      incorrect IRQ override in its ACPI tables, for example because the
      responsible block has been blindly copied from a machine using a commoner
      wiring.  This could be moderately easily fixed up with a quirk based on
      the PCI ID (after checking it again, we actually used to have a quirk for
      ATI in this area, but the way it was done suggests the issue was not
      understood well enough).
      
       Could you please remove the hack sent yesterday and test the patch
      provided below?  I do hope it builds, but I have no immediate means to
      check it.  Please report the output.  The intent is to test INTIN0
      directly before testing INTIN2 through the 8259A.  Thanks.
      
       Aside of that, what I have gathered from your reports (please correct me
      if I have got it wrong) is that when the through-8259A mode is used, then
      after a while 8254 timer interrupts stop arriving.  What's interesting,
      the "Virtual Wire IRQ" seems to work for you correctly (that's quite an
      odd setup where a local APIC input is used in the native mode -- please
      post /proc/interrupts for confirmation), which in turn implies the master
      8259A drives its INT output as we expect.  Why would the I/O APIC input
      have problems then?  Hmm...
      
      [ mingo@elte.hu: revert the "x86: fix IO APIC breakage on HP nx6325"
        version. ]
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      7f0dbbc0
    • M
      x86: fix IO APIC breakage on HP nx6325 · cd08d075
      Maciej W. Rozycki 提交于
      On Thu, 19 Jun 2008, Rafael J. Wysocki wrote:
      
      > >  With such a configuration the "x86: I/O APIC: timer through 8259A
      > > second-chance" patch should not matter, because the only change it
      > > introduces is an attempt to try the same I/O APIC pin again, but with the
      > > IRQ0 line of the master 8259A enabled.  That's not a terribly unusual
      > > configuration and nothing should get confused in the system.
      >
      > But it _does_ get confused, really.
      
       Something certainly gets confused, but so far I am not sure which bit
      exactly it is, are you?
      
      > >  Barring the unlikely possibility of the 8259A actually being wired to
      > > INTIN2 of the I/O APIC I can see two possible explanations:
      > >
      > > 1. The 8259A interrupt actually escapes to the CPU somehow and is handled
      > >    as an ExtINTA interrupt.  This would make the code in check_timer()
      > >    decide it has found a working configuration, while actually it has been
      > >    fooled.
      [...]
      > Here you go:
      >
      > [    0.108006] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
      > [    0.108006] ..MP-BIOS bug: 8254 timer not connected to IO-APIC
      > [    0.108006] ...trying to set up timer (IRQ0) through the 8259A ... <3>
      > [    0.108006] ..... (found apic 0 pin 2) ...<3> works.
      >
      > The full dmesg is at: http://www.sisk.pl/kernel/debug/20080618/dmesg-1.log
      
      Thanks.  In this case I suspect the case #1 quoted above happens, that is
      the 8259A manages to deliver its interrupt somehow.  Note at this stage it
      is meant to be in the AEOI mode, so it can happily resubmit the interrupt
      indefinitely with no additional handling as long as it receives INTA
      cycles.
      
      Can you please try the patch below on top of "x86: I/O APIC: timer
      through 8259A second-chance" to see whether my hypothesis is true?  It
      modifies the through-8259A setup path so that the APIC input gets masked,
      but the 8259A has the timer interrupt still enabled.  Let me know how the
      timer interrupt is routed in this case.
      Bisected-by: N"Rafael J. Wysocki" <rjw@sisk.pl>
      Tested-by: N"Rafael J. Wysocki" <rjw@sisk.pl>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      cd08d075
    • C
      x86, io-apic: use predefined names instead of numeric constants · 46b3b4ef
      Cyrill Gorcunov 提交于
      This patch replaces some hard-coded numbers with predefined names.
      Signed-off-by: NCyrill Gorcunov <gorcunov@gmail.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      46b3b4ef
    • C
      x86: IO-APIC - use NMI_NONE instead of numeric constant · 067fa0ff
      Cyrill Gorcunov 提交于
      Not sure but maybe it is better to use NMI_DISABLED,
      will take a look. But for now this patch is not change
      anything in logic so it will not hurt/broke the kernel.
      For most cases nmi_watchdog assignment is by one of NMI_*
      macro so I think there it make sense too.
      Signed-off-by: NCyrill Gorcunov <gorcunov@gmail.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      067fa0ff
    • I
      x86 build fix: · b1b57ee1
      Ingo Molnar 提交于
        arch/x86/kernel/io_apic_64.c: In function 'check_timer':
        arch/x86/kernel/io_apic_64.c:1688: error: 'vector' undeclared (first use in this function)
        arch/x86/kernel/io_apic_64.c:1688: error: (Each undeclared identifier is reported only once
        arch/x86/kernel/io_apic_64.c:1688: error: for each function it appears in.)
      b1b57ee1
    • T
      x86: make irq_cfg static · 7223daf5
      Thomas Gleixner 提交于
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      7223daf5
    • M
      x86: I/O APIC: timer through 8259A second-chance · 691874fa
      Maciej W. Rozycki 提交于
      Some systems incorrectly report the ExtINTA pin of the I/O APIC as the
      genuine target of the timer interrupt.  Here is a change that copies timer
      pin information found to the other pin if one has been found only.  This
      way both a direct and a through-8259A route is tested with the pin letting
      these problematic systems work well enough.  If no timer pin information
      has been found for the I/O APIC, then local APIC variations are tried
      only, similarly to what is done without the change (except without the
      misleading messages).
      
      Obviously if we try the first-chance path without being told by the BIOS
      to do so, we should not complain either, so do not print the message in
      this case.
      
      The 64-bit variation should be updated with a call to
      replace_pin_at_irq() which can be done with the upcoming merge.  Since
      add_pin_to_irq() is now always called in the first-chance path, the
      condition to require it in the second-chance path no longer happens.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      691874fa
    • M
      x86: I/O APIC: keep the timer IRQ masked during set-up · 03be7505
      Maciej W. Rozycki 提交于
      Keep the timer interrupt line masked when reconfiguring its interrupt
      redirection entry in the I/O APIC.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      03be7505
    • M
      x86: I/O APIC: unmask the second-chance timer interrupt · 24742ece
      Maciej W. Rozycki 提交于
      Unmask the timer interrupt line set up in the through-8259A mode
      explicitly after setup_timer_IRQ0_pin() has set up the I/O APIC interrupt
      redirection entry to let the two operations be unbound from each other.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      24742ece
    • M
      x86: I/O APIC: rename setup_ExtINT_IRQ0_pin() · f7633ce5
      Maciej W. Rozycki 提交于
      Rename setup_ExtINT_IRQ0_pin() to setup_timer_IRQ0_pin() to better
      reflect the upcoming role of a function setting up a (semi-)arbitrary I/O
      APIC pin appropriately for the 8254 timer.  By "appropriate" the following
      settings are meant: edge-triggered, active-high, all the other settings
      per-architecture.  Adjust comments to reflect code appropriately.  No
      functional changes.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      f7633ce5
    • M
      x86: I/O APIC: remove redundant LVT0 masking · 6b4722a7
      Maciej W. Rozycki 提交于
      The LINT0 line of the local APIC is masked in the LVT0 entry in
      check_timer() before this function is ever called.  Removed the
      redundant unmasking for better control.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      6b4722a7
    • M
      x86: I/O APIC: remove redundant 8259A {,un}masking · 80d16bac
      Maciej W. Rozycki 提交于
      For a better control the masking and unmasking of the timer interrupt
      line in the 8259A operating in the 'Virtual Wire' mode has been moved out
      of setup_ExtINT_IRQ0_pin() now, so remove the redundant calls from the
      function.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      80d16bac
    • M
      x86: I/O APIC: clean up the 8259A on a NMI watchdog failure · 35542c5e
      Maciej W. Rozycki 提交于
      There is no point in keeping the 8259A enabled if the I/O APIC NMI
      watchdog has failed and the 8259A is not used to pass through regular
      timer interrupts.  This fixes problems with some systems where some logic
      gets confused.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      35542c5e
    • M
      x86: I/O APIC: keep IRQ off when changing LVT registers · 60134ebe
      Maciej W. Rozycki 提交于
      Disable the 8259A acting in the "virtual wire" mode to keep the interrupt
      line inactive while fiddling with local APIC interrupt vector registers
      associated with its destination inputs.  To be on the safe side,
      especially concerning flipping the trigger mode.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      60134ebe
    • M
      x86: I/O APIC: clean up after a fasteoi failure · e67465f1
      Maciej W. Rozycki 提交于
      Disable the 8259A when routing of the timer interrupt through the chip to
      the local APIC of the primary processor has failed.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      e67465f1
    • M
      x86: I/O APIC: remove parameters to fiddle with the 8259A · ecd29476
      Maciej W. Rozycki 提交于
      Remove the "disable_8254_timer" and "enable_8254_timer" kernel
      parameters.  Now that AEOI acknowledgements are no longer needed for
      correct timer operation, the 8259A can be kept disabled unconditionally
      unless interrupts, either timer or watchdog ones, are actually passed
      through it.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      ecd29476
    • M
      x86: I/O APIC: AEOI timer acknowledgement clean-ups · d11d5794
      Maciej W. Rozycki 提交于
      The code that used to be in do_slow_gettimeoffset() that relied on the
      IRR bit of the master 8259A PIC for IRQ0 to check the state of the output
      timer 0 of the PIT is no longer there.  As a result, there is no need to
      use the POLL command to acknowledge the timer interrupt in the "8259A
      Virtual Wire", except for the NMI watchdog when the i82489DX APIC is used
      (this is because this particular APIC treats NMIs as level-triggered and
      keeping the input asserted would keep motherboard NMI sources held off for
      too long).  Remove the unneeded bits and adjust comments accordingly.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      d11d5794
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