- 10 6月, 2014 12 次提交
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由 Christian König 提交于
v2: agd5f: simplify patch Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Christian König 提交于
And also domain to prefered_domains. That matches better what those values represent. Signed-off-by: NChristian König <christian.koenig@amd.com> Cc: Marek Olšák <maraeo@gmail.com> Reviewed-by: NMarek Olšák <marek.olsak@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Christian König 提交于
The underlying reason for the crashes seems to be fixed now. Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Christian König 提交于
We never check the return value anyway and if the index isn't valid would crash way before calling the functions. Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Christian König 提交于
When we set the valid bit on invalid GART entries they are loaded into the TLB when an adjacent entry is loaded. This poisons the TLB with invalid entries which are sometimes not correctly removed on TLB flush. For stable inclusion the patch probably needs to be modified a bit. Signed-off-by: NChristian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Mario Kleiner 提交于
Make sure that a hdmi deep color mode can't exceed the max tmds clock limit of a hdmi sink if such a limit is defined by edid. If requested deep color bpc would exceed the limit given the mode to be set, try to degrade gracefully to lower supported deep color bpc or to standard 8 bpc if needed. Signed-off-by: NMario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Mario Kleiner 提交于
HDMI deep color setup must know which modes are supported if it needs to degrade gracefully, as only 12 bpc / dc_36 is guaranteed, but 10 bpc / dc_30 is optional. The maximum bpc is not sufficient for this. Signed-off-by: NMario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
Hawaii has the same version of VCE as other CIK parts. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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由 Christian König 提交于
Replace occurrences of "v & 0xffffffff" with lower_32_bits(v) when it's next to an upper_32_bits(v). Also remove unnecessary "upper_32_bits(v) & 0xffffffff" code snippets. Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Damien Lespiau 提交于
Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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git://anongit.freedesktop.org/tegra/linux由 Dave Airlie 提交于
drm/panel: Changes for v3.16-rc1 This set of commits contains a couple of fixes to existing panel drivers and support for some new panels. One commit touches the DRM core in that in modifies the MIPI DSI support to hook up the shutdown function so that drivers can provide code that's run on shutdown. This is used by a subsequent commit to make the simple panel driver power off the backlight on shutdown. * tag 'drm/panel/for-3.16-rc1' of git://anongit.freedesktop.org/tegra/linux: drm/panel: simple - Add AUO B133XTN01 panel support drm/panel: simple - Disable panel on shutdown drm/panel: add support for EDT ET057090DHU panel drm/panel: Add support for EDT ETM0700G0DH6 and ET070080DH6 panels drm/panel: ld9040: add power control sequence drm/panel: s6e8aa0: silence array overflow warning drm/dsi: Support device shutdown
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git://anongit.freedesktop.org/tegra/linux由 Dave Airlie 提交于
drm/tegra: Changes for v3.16-rc1 The majority of these changes are a slew of cleanups across the board. A more noteworthy change is the addition of drm_dev_set_unique() and the conversion of the Tegra DRM driver to use it. This allows us to get rid of the host1x drm_bus implementation. Other USB and platform drivers can be changed in a similar way. Unfortunately for most PCI devices there is some userspace that relies on the old functionality and cannot be as easily converted. HDMI and hardware cursor support is added for Tegra124. The SOR output gains support for exposing CRCs via debugfs, which can be used for automated testing. Many values that were hardcoded in the SOR/eDP code are now computed at runtime to increase compatibility with more devices. * tag 'drm/tegra/for-3.16-rc1' of git://anongit.freedesktop.org/tegra/linux: (47 commits) drm/tegra: sor - Remove obsolete comment drm/tegra: sor - Enable only the necessary number of lanes drm/tegra: sor - Power on only the necessary lanes drm/tegra: sor - Do not program interlaced mode registers drm/tegra: sor - Do not hardcode link speed drm/tegra: sor - Do not hardcode number of blank symbols drm/tegra: sor - Don't hardcode link parameters drm/tegra: sor - Change power down ordering drm/tegra: sor - Fix copy/paste error drm/tegra: sor - Remove pixel clock rounding drm/tegra: sor - Make debugfs setup consistent drm/tegra: sor - Recursively remove debugfs tree drm/tegra: dp - Mark the connector as hotplug capable drm/tegra: dp - Implement hotplug detection in work queue drm/tegra: Add hardware cursor support drm/tegra: Remove host1x drm_bus implementation drm: Document how to register devices without struct drm_bus drm: Add device registration documentation drm: Introduce drm_dev_set_unique() gpu: host1x: Rename internal functions for clarity ...
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- 09 6月, 2014 11 次提交
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由 Stéphane Marchesin 提交于
This panel is used by nyan-big and can be supported by the simple-panel driver. Signed-off-by: NStéphane Marchesin <marcheu@chromium.org> [treding@nvidia.com: add device tree binding document] Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
According to the DP specification the disparity of the first symbol should always be negative. It is therefore safe to assume that panels will conform to that and therefore parameterizing this field should never be necessary. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
Instead of always enabling all four lanes, enable only the number probed from the link. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
Power on only those lanes required for the specified link. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
Interlaced mode is currently not supported on the SOR, so don't program any associated registers. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
Use the speed probed from the link at runtime rather than relying on a hardcoded default. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
The number of HBLANK and VBLANK symbols can be computed at runtime so that they can be set appropriately depending on the video mode and DP link. These values are used by the packet generation logic to determine how many audio samples can be transferred during the blanking intervals. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
The currently hardcoded link parameters don't work on all eDP panels, so compute the parameters at runtime depending on the mode and panel type to allow the driver to cope with a wider variety of panels. Note that the number of bits per pixel of the panel is still hardcoded, but this can be addressed in a separate patch. This is largely based on a patch by Stéphane Marchesin but the algorithm was largely rewritten to be more readable and concise. Signed-off-by: NStéphane Marchesin <marcheu@chromium.org> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Stéphane Marchesin 提交于
Lanes are powered up in decreasing order. Power them down in increasing order for consistency. Signed-off-by: NStéphane Marchesin <marcheu@chromium.org> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Stéphane Marchesin 提交于
The comment above mentions link A/B but this isn't what the code does, so let's fix that. Signed-off-by: NStéphane Marchesin <marcheu@chromium.org> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Stéphane Marchesin 提交于
The code currently rounds up the clock to the next MHZ, which is rounding up a 69.5MHz clock to 70MHz on my machine. This in turn prevents the display from syncing. Removing this rounding fixes eDP for me. Signed-off-by: NStéphane Marchesin <marcheu@chromium.org> Signed-off-by: NThierry Reding <treding@nvidia.com>
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- 06 6月, 2014 17 次提交
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git://anongit.freedesktop.org/drm-intel由 Dave Airlie 提交于
> Bunch of stuff for 3.16 still: > - Mipi dsi panel support for byt. Finally! From Shobhit&others. I've > squeezed this in since it's a regression compared to vbios and we've > been ridiculed about it a bit too often ... > - connection_mutex deadlock fix in get_connector (only affects i915). > - Core patches from Matt's primary plane from Matt Roper, I've pushed the > i915 stuff to 3.17. > - vlv power well sequencing fixes from Jesse. > - Fix for cursor size changes from Chris. > - agpbusy fixes from Ville. > - A few smaller things. > * tag 'drm-intel-fixes-2014-06-06' of git://anongit.freedesktop.org/drm-intel: (32 commits) drm/i915: BDW: Adding missing cursor offsets. drm: Fix getconnector connection_mutex locking drm/i915/bdw: Only use 2g GGTT for 32b platforms drm/i915: Nuke pipe A quirk on i830M drm/i915: fix display power sw state reporting drm/i915: Always apply cursor width changes drm/i915: tell the user if both KMS and UMS are disabled drm/plane-helper: Add drm_plane_helper_check_update() (v3) drm: Check CRTC compatibility in setplane drm/i915: use VBT to determine whether to enumerate the VGA port drm/i915: Don't WARN about ring idle bit on gen2 drm/i915: Silence the WARN if the user tries to GTT mmap an incoherent object drm/i915: Move the C3 LP write bit setup to gen3_init_clock_gating() for KMS drm/i915: Enable interrupt-based AGPBUSY# enable on 85x drm/i915: Flip the sense of AGPBUSY_DIS bit drm/i915: Set AGPBUSY# bit in init_clock_gating drm/i915/vlv: add pll assertion when disabling DPIO common well drm/i915/vlv: move DPIO common reset de-assert into __vlv_set_power_well drm/i915/vlv: re-order power wells so DPIO common comes after TX drm/i915/vlv: move CRI refclk enable into __vlv_set_power_well ...
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由 Thierry Reding 提交于
Other output drivers set up debugfs slightly differently. Bring the SOR driver in line with those for consistency. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
Removing only the root directory will fail when there are still files in it. Instead of manually removing all files, remove the whole directory recursively. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
Doing so allows the hotplug events generated by the connector to be properly handled by the DRM poll helpers. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
Calling the drm_helper_hpd_irq_event() helper can sleep, so instead of invoking it directly from the interrupt handler, schedule a work queue and run it from there. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
Enable hardware cursor support on Tegra124. Earlier generations support the hardware cursor to some degree as well, but not in a way that can be generically exposed. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
The DRM core can now cope with drivers that don't have an associated struct drm_bus, so the host1x implementation is no longer useful. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
With the recent addition of the drm_set_unique() function, devices can now be registered without requiring a drm_bus. Add a brief description to the DRM docbook to show how that can be achieved. Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
Describe how devices are registered using the drm_*_init() functions. Adding this to docbook requires a largish set of changes to the comments in drm_{pci,usb,platform}.c since they are doxygen-style rather than proper kernel-doc and therefore mess with the docbook generation. While at it, mark usage of drm_put_dev() as discouraged in favour of calling drm_dev_unregister() and drm_dev_unref() directly. Acked-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
Add a helper function that allows drivers to statically set the unique name of the device. This will allow platform and USB drivers to get rid of their DRM bus implementations and directly use drm_dev_alloc() and drm_dev_register(). Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: NDavid Herrmann <dh.herrmann@gmail.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
The internal host1x_{,un}register_client() functions can potentially be confused with public the host1x_client_{,un}register() functions. Rename them to host1x_{add,del}_client() to remove some of the possible confusion. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
The function is never used outside of the source file and therefore can be locally scoped. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
Tegra124 is mostly backwards-compatible with Tegra114. However, Tegra124 supports a few more features (e.g. interlacing, ...). Introduce a new compatible string and TMDS tables to cope with these differences. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
Accessing the CRC debugfs file will hang the system if the SOR is not enabled, so make sure that it is stays enabled until the CRC has been read. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
In some cases the pixel clock used to not be correct, which is why it had to be recomputed. It turns out that the reason why it wasn't correct is that it was used wrongly. If used correctly there's not need for the recomputation. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
The shift clock divider is highly dependent on the type of output, so push computation of it down into the output drivers. The old code used to work merely by accident. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
Program the shift clock divider in tegra_crtc_setup_clk() since that's where the divider is computed, so passing it around can be avoided. Signed-off-by: NThierry Reding <treding@nvidia.com>
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