1. 21 10月, 2014 1 次提交
    • P
      pinctrl: st: Fix Sparse error · 2e537276
      Pramod Gurav 提交于
      This change fixes below sparse error,
      drivers/pinctrl/pinctrl-st.c:1515:31: error: incompatible types for operation (>)
      drivers/pinctrl/pinctrl-st.c:1515:31:    left side has type void [noderef] <asn:2>*irqmux_base
      drivers/pinctrl/pinctrl-st.c:1515:31:    right side has type int
      
      Cc: Maxime Coquelin <maxime.coquelin@st.com>
      Cc: Patrice Chotard <patrice.chotard@st.com>
      CC: Linus Walleij <linus.walleij@linaro.org>
      Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
      Signed-off-by: NPramod Gurav <pramod.gurav@smartplayin.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      2e537276
  2. 23 9月, 2014 1 次提交
  3. 04 9月, 2014 1 次提交
  4. 16 7月, 2014 1 次提交
    • M
      pinctrl: st: Fix irqmux handler · 7a2deccf
      Maxime COQUELIN 提交于
      st_gpio_irqmux_handler() reads the status register to find out
      which banks inside the controller have pending IRQs.
      For each banks having pending IRQs, it calls the corresponding handler.
      
      Problem is that current code restricts the number of possible banks inside the
      controller to ST_GPIO_PINS_PER_BANK. This define represents the number of pins
      inside a bank, so it shouldn't be used here.
      
      On STiH407, PIO_FRONT0 controller has 10 banks, so IRQs pending in the two
      last banks (PIO18 & PIO19) aren't handled.
      
      This patch replace ST_GPIO_PINS_PER_BANK by the number of banks inside the
      controller.
      
      Cc: Linus Walleij <linus.walleij@linaro.org>
      Cc: <stable@vger.kernel.org> #v3.15+
      Acked-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
      Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      7a2deccf
  5. 11 7月, 2014 4 次提交
    • R
      pinctrl: pinctrl-st.c: Cleaning up values that are never used · 1f978217
      Rickard Strandqvist 提交于
      Remove variable that are never used
      
      This was found using a static code analysis program called cppcheck.
      Signed-off-by: NRickard Strandqvist <rickard_strandqvist@spectrumdigital.se>
      Acked-by: NPatrice Chotard <patrice.chotard@st.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      1f978217
    • R
      pinctrl: pinctrl-st.c: Cleaning up if unsigned is less than zero · 8b0c107c
      Rickard Strandqvist 提交于
      Remove checking if a unsigned is less than zero
      
      This was found using a static code analysis program called cppcheck.
      Signed-off-by: NRickard Strandqvist <rickard_strandqvist@spectrumdigital.se>
      Acked-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
      Acked-by: NMaxime Coquelin <maxime.coquelin@st.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      8b0c107c
    • D
      pinctrl: st: add IRQCHIP_SKIP_SET_WAKE flag · 8708ebca
      David PARIS 提交于
      no .irq_set_wake API is available for pinctrl-st driver.
      Add the IRQCHIP_SKIP_SET_WAKE flag to inform irq handler
      not to call this API.
      Signed-off-by: NDavid Paris <david.paris@st.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      8708ebca
    • F
      pinctrl: avoid duplicated calling enable_pinmux_setting for a pin · 2243a87d
      Fan Wu 提交于
      What the patch does:
      1. Call pinmux_disable_setting ahead of pinmux_enable_setting
        each time pinctrl_select_state is called
      2. Remove the HW disable operation in pinmux_disable_setting function.
      3. Remove the disable ops in struct pinmux_ops
      4. Remove all the disable ops users in current code base.
      
      Notes:
      1. Great thanks for the suggestion from Linus, Tony Lindgren and
         Stephen Warren and Everyone that shared comments on this patch.
      2. The patch also includes comment fixes from Stephen Warren.
      
      The reason why we do this:
      1. To avoid duplicated calling of the enable_setting operation
         without disabling operation inbetween which will let the pin
         descriptor desc->mux_usecount increase monotonously.
      2. The HW pin disable operation is not useful for any of the
         existing platforms.
         And this can be used to avoid the HW glitch after using the
         item #1 modification.
      
      In the following case, the issue can be reproduced:
      1. There is a driver that need to switch pin state dynamically,
         e.g. between "sleep" and "default" state
      2. The pin setting configuration in a DTS node may be like this:
      
        component a {
      	pinctrl-names = "default", "sleep";
      	pinctrl-0 = <&a_grp_setting &c_grp_setting>;
      	pinctrl-1 = <&b_grp_setting &c_grp_setting>;
        }
      
        The "c_grp_setting" config node is totally identical, maybe like
        following one:
      
        c_grp_setting: c_grp_setting {
      	pinctrl-single,pins = <GPIO48 AF6>;
        }
      
      3. When switching the pin state in the following official pinctrl
         sequence:
      	pin = pinctrl_get();
      	state = pinctrl_lookup_state(wanted_state);
      	pinctrl_select_state(state);
      	pinctrl_put();
      
      Test Result:
      1. The switch is completed as expected, that is: the device's
         pin configuration is changed according to the description in the
         "wanted_state" group setting
      2. The "desc->mux_usecount" of the corresponding pins in "c_group"
         is increased without being decreased, because the "desc" is for
         each physical pin while the setting is for each setting node
         in the DTS.
         Thus, if the "c_grp_setting" in pinctrl-0 is not disabled ahead
         of enabling "c_grp_setting" in pinctrl-1, the desc->mux_usecount
         will keep increasing without any chance to be decreased.
      
      According to the comments in the original code, only the setting,
      in old state but not in new state, will be "disabled" (calling
      pinmux_disable_setting), which is correct logic but not intact. We
      still need consider case that the setting is in both old state
      and new state. We can do this in the following two ways:
      
      1. Avoid to "enable"(calling pinmux_enable_setting) the "same pin
         setting" repeatedly
      2. "Disable"(calling pinmux_disable_setting) the "same pin setting",
         actually two setting instances, ahead of enabling them.
      
      Analysis:
      1. The solution #2 is better because it can avoid too much
         iteration.
      2. If we disable all of the settings in the old state and one of
         the setting(s) exist in the new state, the pins mux function
         change may happen when some SoC vendors defined the
         "pinctrl-single,function-off"
         in their DTS file.
         old_setting => disabled_setting => new_setting.
      3. In the pinmux framework, when a pin state is switched, the
         setting in the old state should be marked as "disabled".
      
      Conclusion:
      1. To Remove the HW disabling operation to above the glitch mentioned
         above.
      2. Handle the issue mentioned above by disabling all of the settings
         in old state and then enable the all of the settings in new state.
      Signed-off-by: NFan Wu <fwu@marvell.com>
      Acked-by: NStephen Warren <swarren@nvidia.com>
      Acked-by: NPatrice Chotard <patrice.chotard@st.com>
      Acked-by: NHeiko Stuebner <heiko@sntech.de>
      Acked-by: NMaxime Coquelin <maxime.coquelin@st.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      2243a87d
  6. 22 4月, 2014 4 次提交
  7. 12 3月, 2014 4 次提交
  8. 10 2月, 2014 2 次提交
  9. 15 1月, 2014 1 次提交
  10. 28 8月, 2013 1 次提交
  11. 08 8月, 2013 2 次提交
  12. 30 6月, 2013 1 次提交
  13. 28 6月, 2013 1 次提交
  14. 25 6月, 2013 1 次提交
    • S
      pinctrl: st: Add pinctrl and pinconf support. · 701016c0
      Srinivas KANDAGATLA 提交于
      This patch add pinctrl support to ST SoCs.
      
      About hardware:
      ST Set-Top-Box parts have two blocks called PIO and PIO-mux which handle
      pin configurations.
      
      Each multi-function pin is controlled, driven and routed through the PIO
      multiplexing block. Each pin supports GPIO functionality (ALT0) and
      multiple alternate functions(ALT1 - ALTx) that directly connect the pin
      to different hardware blocks. When a pin is in GPIO mode, Output Enable
      (OE), Open Drain(OD), and Pull Up (PU) are driven by the related PIO
      block. Otherwise the PIO multiplexing block configures these parameters
      and retiming the signal.
      
      About driver:
      This pinctrl driver manages both PIO and PIO-mux block using pinctrl,
      pinconf, pinmux, gpio subsystems. All the pinctrl related config
      information can only come from device trees.
      Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@st.com>
      Acked-by: NLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: NMark Brown <broonie@linaro.org>
      701016c0