1. 25 10月, 2015 1 次提交
    • D
      i2c: add ACPI support for I2C mux ports · 8eb5c87a
      Dustin Byford 提交于
      Although I2C mux devices are easily enumerated using ACPI (_HID/_CID or
      device property compatible string match), enumerating I2C client devices
      connected through an I2C mux needs a little extra work.
      
      This change implements a method for describing an I2C device hierarchy that
      includes mux devices by using an ACPI Device() for each mux channel along
      with an _ADR to set the channel number for the device.  See
      Documentation/acpi/i2c-muxes.txt for a simple example.
      
      To make this work the ismt, i801, and designware pci/platform devs now
      share an ACPI companion with their I2C adapter dev similar to how it's done
      in OF.  This is done on the assumption that power management functions will
      not be called directly on the I2C dev that is sharing the ACPI node.
      Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com>
      Tested-by: NMika Westerberg <mika.westerberg@linux.intel.com>
      Signed-off-by: NDustin Byford <dustin@cumulusnetworks.com>
      Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      8eb5c87a
  2. 24 10月, 2015 2 次提交
  3. 11 8月, 2015 1 次提交
  4. 09 3月, 2015 5 次提交
  5. 13 11月, 2014 1 次提交
  6. 12 11月, 2014 4 次提交
  7. 08 11月, 2014 1 次提交
  8. 16 10月, 2014 1 次提交
  9. 19 8月, 2014 1 次提交
  10. 18 7月, 2014 2 次提交
  11. 13 3月, 2014 1 次提交
  12. 10 3月, 2014 1 次提交
  13. 30 1月, 2014 1 次提交
  14. 15 11月, 2013 1 次提交
  15. 23 8月, 2013 1 次提交
    • W
      i2c: move OF helpers into the core · 687b81d0
      Wolfram Sang 提交于
      I2C of helpers used to live in of_i2c.c but experience (from SPI) shows
      that it is much cleaner to have this in the core. This also removes a
      circular dependency between the helpers and the core, and so we can
      finally register child nodes in the core instead of doing this manually
      in each driver. So, fix the drivers and documentation, too.
      Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      687b81d0
  16. 21 6月, 2013 1 次提交
  17. 18 5月, 2013 1 次提交
  18. 22 2月, 2013 1 次提交
  19. 16 2月, 2013 1 次提交
  20. 09 2月, 2013 1 次提交
  21. 23 12月, 2012 1 次提交
  22. 17 12月, 2012 2 次提交
  23. 29 10月, 2012 2 次提交
  24. 06 10月, 2012 2 次提交
    • J
      i2c-i801: Let i2c-mux-gpio find the GPIO chip · f82b8626
      Jean Delvare 提交于
      Now that i2c-mux-gpio is able to find the GPIO chip by itself, we can
      delegate this task. The great thing here is that i2c-mux-gpio can
      defer device probing until the gpio chip is available, so we no longer
      depend on the module loading order.
      Signed-off-by: NJean Delvare <khali@linux-fr.org>
      f82b8626
    • J
      i2c-i801: Support SMBus multiplexing on Asus Z8 series · 3ad7ea18
      Jean Delvare 提交于
      Add support for SMBus multiplexing on Asus Z8 motherboard series. On
      these boards, the memory slots are behind a GPIO-controlled I2C
      multiplexer. Models with 6 or 12 memory slots have 2 segments behind
      the multiplexer, while models with 18 memory slots have 3 such
      segments.
      
      On these boards, only the memory slots are behind the multiplexer,
      so it is possible to keep the autodetection mechanism.
      
      The code is generic enough so it could work on other boards as long as
      the multiplexer is controlled by GPIO pins. For other forms of
      multiplexing (for example using an I2C device) additional code will be
      needed.
      
      Thanks to Asus for providing a board to develop and test this feature,
      as well as all the technical information required.
      
      At the moment, the GPIO driver must be loaded before the i2c-i801
      driver, but I hope to solve this soon, using deferred probing on
      the i2c-mux-gpio side.
      Signed-off-by: NJean Delvare <khali@linux-fr.org>
      3ad7ea18
  25. 10 9月, 2012 1 次提交
  26. 24 7月, 2012 3 次提交
    • D
      i2c-i801: Enable IRQ for byte_by_byte transactions · d3ff6ce4
      Daniel Kurtz 提交于
      Byte-by-byte transactions are used primarily for accessing I2C devices
      with an SMBus controller.  For these transactions, for each byte that is
      read or written, the SMBus controller generates a BYTE_DONE IRQ.  The isr
      reads/writes the next byte, and clears the IRQ flag to start the next byte.
      On the penultimate IRQ, the isr also sets the LAST_BYTE flag.
      
      There is no locking around the cmd/len/count/data variables, since the
      I2C adapter lock ensures there is never multiple simultaneous transactions
      for the same device, and the driver thread never accesses these variables
      while interrupts might be occurring.
      
      The end result is faster I2C block read and write transactions.
      
      Note: This patch has only been tested and verified by doing I2C read and
      write block transfers on Cougar Point 6 Series PCH, as well as I2C read
      block transfers on ICH5.
      Signed-off-by: NDaniel Kurtz <djkurtz@chromium.org>
      Signed-off-by: NJean Delvare <khali@linux-fr.org>
      d3ff6ce4
    • J
      i2c-i801: Enable interrupts on ICH5/7/8/9/10 · 29b60854
      Jean Delvare 提交于
      Enable interrupts on more devices. ICH5, ICH7(-M) and ICH10 have been
      tested to work OK. ICH8 and ICH9 are expected to work just fine as
      they are very close to ICH7 and ICH10.
      
      Ultimately we want to enable this feature on at least every device
      since the ICH5, but for now we limit the exposure. We'll enable it for
      other devices if we don't get negative feedback.
      
      As a bonus, let the user know when interrupts are used.
      Signed-off-by: NJean Delvare <khali@linux-fr.org>
      Cc: Daniel Kurtz <djkurtz@chromium.org>
      29b60854
    • D
      i2c-i801: Enable IRQ for SMBus transactions · 636752bc
      Daniel Kurtz 提交于
      Add a new 'feature' to i2c-i801 to enable using PCI interrupts.
      When the feature is enabled, then an isr is installed for the device's
      PCI IRQ.
      
      An I2C/SMBus transaction is always terminated by one of the following
      interrupt sources: FAILED, BUS_ERR, DEV_ERR, or on success: INTR.
      
      When the isr fires for one of these cases, it sets the ->status variable
      and wakes up the waitq.  The waitq then saves off the status code, and
      clears ->status (in preparation for some future transaction).
      The SMBus controller generates an INTR irq at the end of each
      transaction where INTREN was set in the HST_CNT register.
      
      No locking is needed around accesses to priv->status since all writes to
      it are serialized: it is only ever set once in the isr at the end of a
      transaction, and cleared while no interrupts can occur.  In addition, the
      I2C adapter lock guarantees that entire I2C transactions for a single
      adapter are always serialized.
      
      For this patch, the INTREN bit is set only for SMBus block, byte and word
      transactions, but not for I2C reads or writes.  The use of the DS
      (BYTE_DONE) interrupt with byte-by-byte I2C transactions is implemented in
      a subsequent patch.
      
      The interrupt feature has only been enabled for COUGARPOINT hardware.
      In addition, it is disabled if SMBus is using the SMI# interrupt.
      Signed-off-by: NDaniel Kurtz <djkurtz@chromium.org>
      Signed-off-by: NJean Delvare <khali@linux-fr.org>
      636752bc