Add the Miscellaneous System Control Module (MSCM) to the base
device tree for Vybrid SoC's. This module contains registers
to get information of the individual and current (accessing)
CPU. In a second block, there is an interrupt router, which
handles the routing of the interrupts between the two CPU cores
on VF6xx variants of the SoC. However, also on single core
variants the interrupt router needs to be configured in order
to receive interrupts on the CPU's interrupt controller. Almost
all peripheral interrupts are routed through the router, hence
the MSCM module is the default interrupt parent for this SoC.

In a earlier commit the interrupt nodes were moved out of the
peripheral nodes and specified in the CPU specific vf500.dtsi
device tree. This allowed to use the base device tree vfxxx.dtsi
also for a Cortex-M4 specific device tree, which uses different
interrupt nodes due to the NVIC interrupt controller. However,
since the interrupt parent for peripherals is the MSCM module
independently which CPU the device tree is used for, we can move
the interrupt nodes into the base device tree vfxxx.dtsi again.
Depending on which CPU this base device tree will be used with,
the correct parent interrupt controller has to be assigned to
the MSCM-IR node (GIC or NVIC). The driver takes care of the
parent interrupt controller specific needs (interrupt-cells).
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

USDHC2 port uses all the 8 data signals, so pass the 'bus-width' property
accordingly.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NOtavio Salvador <otavio@ossystems.com.br>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Since PWMs are only useful if they are actually connected to an output pin,
let users enable them explicitly in their device trees where they should
also set up the pin configuration.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

All PWM users should explicitly enable the used PWMs in their device tree
so they can be disabled by default in imx6qdl.dtsi.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

All PWM users should explicitly enable the used PWMs in their device tree
so they can be disabled by default in imx6qdl.dtsi.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The PU regulator is enabled during boot, but not necessarily always-on.
It can be disabled by the generic pm domain framework when the PU power
domain is shut down. The ramp delay of 150 us might be a bit conservative,
the value is taken from the Freescale kernel.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The PGC that is part of GPC controls isolation and power sequencing of the
power domains. The PU power domain will be handled by the generic pm domain
framework. It needs a phandle to the PU regulator to turn off power when
the domain is disabled and a list of clocks to be enabled during powerup
for reset propagation.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The PGC that is part of GPC controls isolation and power sequencing of the
power domains. The PU power domain will be handled by the generic pm domain
framework. It needs a phandle to the PU regulator to turn off power when
the domain is disabled, and a list of phandles to all clocks that must be
enabled during powerup for reset propagation.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The chipidea driver adds an extra line of spam to the log when a
host-only chipidea instance is left set to the default of a dual role
controller.

[    2.010873] ci_hdrc ci_hdrc.1: doesn't support gadget

Set the dr_mode property to host on all the host-only nodes
to avoid this warning.
Signed-off-by: NMatt Porter <mporter@konsulko.com>
Acked-by: NPeter Chen <peter.chen@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The WaRP Board is a Wearable Reference Plaform. The board features:

 - Freescale i.MX6 SoloLite processor with 512MB of RAM
 - Freescale FXOS8700CQ 6-axis Xtrinsic sensor
 - Freescale Kinetis KL16 MCU
 - Freescale Xtrinsic MMA955xL intelligent motion sensing platform

The board implements a hybrid architecture to address the evolving
needs of the wearables market. The platform consists of a main board
and an example daughtercard with the ability to add additional
daughtercards for different usage models.

For more information about the project, visit:

 http://www.warpboard.org/Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The anyway depricated gpio-range-cells property was never used
by the pin controller driver. This patch removes it.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

IMX6 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.

This patch does just this, updating the DT files to actually
reflect what the HW provides.

BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the GPC block is actually the first
interrupt controller in the chain, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs won't even boot.
Tested-by: NStefan Agner <stefan@agner.ch>
Acked-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add support for the CLAA057VC01CW display.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add some defines currently missing, fix ordering to make the list
sorted by (mux_reg, mux_val), make sure pins are grouped by mux_reg.

The same definitions are missing from the old pinmux header
(arch/arm/mach-imx/iomux-mx25.h) but as only legacy machine support uses
that and therefor the existing list is obviously good enough I didn't
spend the effort to add the corresponding definitions there, too.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Noticed while looking over the pad definitions. None of the bogus
definitions is used in-tree.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

It may be useful to disable the internal rtc snvs-rtc because an
external rtc is available. This patch adds a label so that board files
can disable this rtc.
Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NGwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>
Signed-off-by: NSebastien Szymanski <sebastien.szymanski@armadeus.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NGwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>
Signed-off-by: NSebastien Szymanski <sebastien.szymanski@armadeus.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NGwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>
Signed-off-by: NSebastien Szymanski <sebastien.szymanski@armadeus.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NGwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>
Signed-off-by: NSebastien Szymanski <sebastien.szymanski@armadeus.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NGwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>
Signed-off-by: NSebastien Szymanski <sebastien.szymanski@armadeus.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The MIPI DSI node contains some ports which represent possible DRM CRTCs
it can connect with.  Each port has a 'reg' property embedded.  This
property will be wrongly interpretted by the MIPI DSI bus driver, because
the driver will take each subnode which contains a 'reg' property as a
DSI peripheral device.  This patch moves the existing MIPI DSI ports into
a new 'ports' node so that the MIPI DSI bus driver may distinguish its
DSI peripheral device(s) from the existing ports.
Acked-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NLiu Ying <Ying.Liu@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Since imx6sx-sdb reva board is experimental and will not be used
formally (eg, no software release based on it), we set revb board
as the formal imx6sx-sdb board.

The imx6sx-sdb uses pfuse200 as pmic which has only one power supply
for both VDDARM_IN and VDDSOC_IN, so VDDARM_IN and VDDSOC_IN have to
use the same (higher one in the same frequency) one as its power supply,
that's the reason we override the OPP setting in board dts file.
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The imx6sx sdb board has two revisions, the current mainline one
is reva which is experimental and mainly for internal use. In
this commit, we rename imx6sx-sdb.dts to imx6sx-sdb.dtsi, and
move the reva dedicated contents to imx6sx-sdb-reva.dts.
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

MCP2515 CAN controller is available on Colibri Evaluation board.
Hence enable MCP2515 CAN.
Acked-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NBhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NBhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Acked-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

We do not have CONFIG_MACH_MX25_3DS platform anymore, so update the defconfig.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

platform-imxdi_rtc.c is only used by mx25, so it can safely go away now that
mx25 has been converted to dt.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

As mx25 has been converted to a dt-only platform, we do not need the "mx25.h"
header file anymore.

Remove it and also clean up all the mx25 occurences from the platform helper
code.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

We use dynamic memory mapping when using dt, so remove all the static mappings.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

We should use dt to retrieve the IIM base address.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

mx25_clocks_init() is only used to register the clocks for non-dt platforms.

As mx25 has been converted to a dt-only platform, we can safely remove it.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Depend the MXC debug board on machines which actually support it.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

As mx25 is a dt-only platform, we can get rid of platform code support files,
which are unused now.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

As there is no more mx25 board files, we can turn mx25 into a dt-only platform.

Rename imx25-dt.c to mach-imx25.c to be consistent with the other i.MX SoCs.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

eukrea mx25 is well supported in device tree, so let's get rid of its board
files.

Cc: Eric Bénard <eric@eukrea.com>
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

When generic pm domain support is enabled, the PGC can be used
to completely gate power to the PU power domain containing GPU3D,
GPU2D, and VPU cores.
This code triggers the PGC powerdown sequence to disable the GPU/VPU
isolation cells and gate power and then disables the PU regulator.
To reenable, the reverse powerup sequence is triggered after the PU
regulator is enabled again.
The GPU and VPU devices in the PU power domain temporarily need
to be clocked during powerup, so that the reset machinery can work.

[Avoid explicit regulator enabling in probe, unless !PM]
Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The i.MX6 contains a power controller that controls power gating and
sequencing for the SoC's power domains.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>