1. 13 4月, 2011 1 次提交
    • N
      sfc: Use rmb() to ensure reads occur in order · fcfa0604
      Neil Turton 提交于
      Enabling write-combining may also enable read reordering.  The BIU is
      only guaranteed to read from a 128-bit CSR or 64-bit SRAM word when
      the host reads from its lowest address; otherwise the BIU may use the
      latched value.  Therefore we need to reinstate the read memory
      barriers after the first read operation for each CSR or SRAM word.
      
      Signed-off-by; Ben Hutchings <bhutchings@solarflare.com>
      fcfa0604
  2. 05 3月, 2011 1 次提交
    • B
      sfc: Use write-combining to reduce TX latency · 65f0b417
      Ben Hutchings 提交于
      Based on work by Neil Turton <nturton@solarflare.com> and
      Kieran Mansley <kmansley@solarflare.com>.
      
      The BIU has now been verified to handle 3- and 4-dword writes within a
      single 128-bit register correctly.  This means we can enable write-
      combining and only insert write barriers between writes to distinct
      registers.
      
      This has been observed to save about 0.5 us when pushing a TX
      descriptor to an empty TX queue.
      Signed-off-by: NBen Hutchings <bhutchings@solarflare.com>
      65f0b417
  3. 01 3月, 2011 1 次提交
  4. 07 12月, 2010 4 次提交
  5. 25 6月, 2010 2 次提交
  6. 24 10月, 2009 1 次提交