Add PCIe support to the ARTPEC-6 SoC. This uses the existing
pcie-artpec6 driver.
So, all that is needed is device tree entries in the DTS.
Signed-off-by: NNiklas Cassel <niklas.cassel@axis.com>
Signed-off-by: NJesper Nilsson <jespern@axis.com>

The irq affinity is required for pmu interrupts.
Signed-off-by: NLars Persson <larper@axis.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Use the cache settings that were determined to give best performance
on artpec-6 typical workloads.
Signed-off-by: NLars Persson <larper@axis.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Use defines from the clock binding header as clock indexes.
Signed-off-by: NLars Persson <larper@axis.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

The clock binding for the main clock controller was changed to an
indexed controller style binding on request of the clk
maintainers. This updates the dtsi to use the new bindings.
Signed-off-by: NLars Persson <larper@axis.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Relaxed the license on the dtsi to permit use in other projects.
Signed-off-by: NLars Persson <larper@axis.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Initial device tree for the Artpec-6 SoC.
Signed-off-by: NLars Persson <larper@axis.com>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NOlof Johansson <olof@lixom.net>