1. 25 7月, 2005 1 次提交
  2. 11 7月, 2005 4 次提交
  3. 05 7月, 2005 1 次提交
    • D
      [SPARC64]: Add support for IRQ pre-handlers. · 088dd1f8
      David S. Miller 提交于
      This allows a PCI controller to shim into IRQ delivery
      so that DMA queues can be drained, if necessary.
      
      If some bus specific code needs to run before an IRQ
      handler is invoked, the bus driver simply needs to setup
      the function pointer in bucket->irq_info->pre_handler and
      the two args bucket->irq_info->pre_handler_arg[12].
      
      The Schizo PCI driver is converted over to use a pre-handler
      for the DMA write-sync processing it needs when a device
      is behind a PCI->PCI bus deeper than the top-level APB
      bridges.
      
      While we're here, clean up all of the action allocation
      and handling.  Now, we allocate the irqaction as part of
      the bucket->irq_info area.  There is an array of 4 irqaction
      (for PCI irq sharing) and a bitmask saying which entries
      are active.
      
      The bucket->irq_info is allocated at build_irq() time, not
      at request_irq() time.  This simplifies request_irq() and
      free_irq() tremendously.
      
      The SMP dynamic IRQ retargetting code got removed in this
      change too.  It was disabled for a few months now, and we
      can resurrect it in the future if we want.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      088dd1f8
  4. 28 6月, 2005 2 次提交
    • D
      [SPARC64]: Get rid of fast IRQ feature. · 63b61452
      David S. Miller 提交于
      The only real user was the assembler floppy interrupt
      handler, which does not need to be in assembly.
      
      This makes it so that there are less pieces of code which
      know about the internal layout of ivector_table[] and
      friends.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      63b61452
    • D
      [SPARC64]: Avoid membar instructions in delay slots. · b445e26c
      David S. Miller 提交于
      In particular, avoid membar instructions in the delay
      slot of a jmpl instruction.
      
      UltraSPARC-I, II, IIi, and IIe have a bug, documented in
      the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
      
      The long and short of it is that if the IMU unit misses
      on a branch or jmpl, and there is a store buffer synchronizing
      membar in the delay slot, the chip can stop fetching instructions.
      
      If interrupts are enabled or some other trap is enabled, the
      chip will unwedge itself, but performance will suffer.
      
      We already had a workaround for this bug in a few spots, but
      it's better to have the entire tree sanitized for this rule.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      b445e26c
  5. 17 4月, 2005 1 次提交
    • L
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds 提交于
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4