1. 23 10月, 2008 2 次提交
  2. 16 10月, 2008 2 次提交
  3. 23 7月, 2008 1 次提交
    • V
      x86: consolidate header guards · 77ef50a5
      Vegard Nossum 提交于
      This patch is the result of an automatic script that consolidates the
      format of all the headers in include/asm-x86/.
      
      The format:
      
      1. No leading underscore. Names with leading underscores are reserved.
      2. Pathname components are separated by two underscores. So we can
         distinguish between mm_types.h and mm/types.h.
      3. Everything except letters and numbers are turned into single
         underscores.
      Signed-off-by: NVegard Nossum <vegard.nossum@gmail.com>
      77ef50a5
  4. 12 7月, 2008 2 次提交
    • S
      x64, x2apic/intr-remap: IO-APIC support for interrupt-remapping · 89027d35
      Suresh Siddha 提交于
      IO-APIC support in the presence of interrupt-remapping infrastructure.
      
      IO-APIC RTE will be programmed with interrupt-remapping table entry(IRTE)
      index and the IRTE will contain information about the vector, cpu destination,
      trigger mode etc, which traditionally was present in the IO-APIC RTE.
      
      Introduce a new irq_chip for cleaner irq migration (in the process
      context as opposed to the current irq migration in the context of an interrupt.
      interrupt-remapping infrastructure will help us achieve this cleanly).
      
      For edge triggered, irq migration is a simple atomic update(of vector
      and cpu destination) of IRTE and flush the hardware cache.
      
      For level triggered, we need to modify the io-apic RTE aswell with the update
      vector information, along with modifying IRTE with vector and cpu destination.
      So irq migration for level triggered is little  bit more complex compared to
      edge triggered migration. But the good news is, we use the same algorithm
      for level triggered migration as we have today, only difference being,
      we now initiate the irq migration from process context instead of the
      interrupt context.
      
      In future, when we do a directed EOI (combined with cpu EOI broadcast
      suppression) to the IO-APIC, level triggered irq migration will also be
      as simple as edge triggered migration and we can do the irq migration
      with a simple atomic update to IO-APIC RTE.
      
      TBD: some tests/changes needed in the presence of fixup_irqs() for
      level triggered irq migration.
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      89027d35
    • S
      x64, x2apic/intr-remap: ioapic routines which deal with initial io-apic RTE setup · 4dc2f96c
      Suresh Siddha 提交于
      Generic ioapic specific routines which be used later during enabling
      interrupt-remapping.
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      4dc2f96c
  5. 08 7月, 2008 6 次提交
  6. 25 5月, 2008 3 次提交
  7. 26 4月, 2008 1 次提交
  8. 17 4月, 2008 2 次提交
  9. 30 1月, 2008 1 次提交
  10. 11 10月, 2007 1 次提交