Add DT binding documentation for the APMU hardware and add "renesas,apmu"
to the list of enable methods for the ARM cpus.
Signed-off-by: NMagnus Damm <damm+renesas@opensource.se>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NRob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add binding document for Broadcom BCM23550 SoC.

BCM23550 has a Cluster Dormant Control IP block that holds cores
in an idle state. Introduce a new CPU enable method in which the CDC is
accessed to bring the core online.
Signed-off-by: NChris Brand <chris.brand@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Commit 84320e1a
("ARM: BCM: Clean up SMP support for Broadcom Kona") moved the
"secondary-boot-reg" property from the "cpus" node to the individual "cpu"
nodes but negelected to update brcm,bcm11351-cpu-method.txt to match.

bcm11351-cpu-method was apparently never added to the list of methods in
bindings/arm/cpus.txt.

bindings/arm/cpus.txt states that "enable-method" should be a property of
the "cpu" node rather than the "cpus" node.

This patch rectifies these two omissions and one inconsistency.
Signed-off-by: NChris Brand <chris.brand@broadcom.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Currently ARM CPUs DT bindings allows different enable-method value for
PSCI based systems. On ARM 64-bit this property is required and must be
"psci" while on ARM 32-bit systems this property is optional and must
be "arm,psci" if present.

However, "arm,psci" has always been the compatible string for the PSCI
node, and was never intended to be the enable-method. So this is a bug
in the binding and not a deliberate attempt at specifying 32-bit
differently.

This is problematic if 32-bit OS is run on 64-bit system which has
"psci" as enable-method rather than the expected "arm,psci".

So let's unify the value into "psci" and remove support for "arm,psci"
before it finds any users.
Reported-by: NSoby Mathew <Soby.Mathew@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Acked-by: NMark Rutland <mark.rutland@arm.com>
Acked-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

The binding documentation uses both "uVolt" and "uV" for micro-volt.
Improve consistency by settling on "uV".
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NRob Herring <robh@kernel.org>

Document the compatible string for the Kryo family of qcom cpus.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Update arm/cpus.txt to add "brcm,vulcan" CPU. Add documentation
for Broadcom Vulcan boards in arm/bcm/brcm,vulcan-soc.txt
Signed-off-by: NJayachandran C <jchandra@broadcom.com>

This adds an SMP boot method for the ARM RealView reference
designs. We also select HAVE_SMP by default and make it use
SMP_ON_UP so we only need to support one single kernel across
the RealView reference designs when using DT.

The RealViews need to have the SCU (Snoop Control Unit)
activated on boot, and this is now done by looking up its
address from the device tree and initializing it and counting
the available cores.

The RealViews boot by using a magic address register in the
system controller (SYS_FLAGS) to store the boot address,
the ROM will then read this register to the PC when the CPUs
are taken out of WFI. This code uses a handle to the syscon
regmap to access this register.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The dynamic power consumption of a device is proportional to the
square of voltage (V) and the clock frequency (f). It can be expressed as

Pdyn = dynamic-power-coefficient * V^2 * f.

The coefficient represents the running time dynamic power consumption in
units of mw/MHz/uVolt^2 and can be used in the above formula to
calculate the dynamic power in mW.
Signed-off-by: NPunit Agrawal <punit.agrawal@arm.com>
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>

Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NRob Herring <robh@kernel.org>

Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
Northstar Plus CPU to the 32-bit ARM CPU device tree binding
documentation file and create a new binding documentation for
Northstar Plus CPU.
Signed-off-by: NKapil Hali <kapilh@broadcom.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

The dual-core Cortex A7 rk3036 is a bit special in that it does not allow
to control the actual powerdomain of the cpu cores, while the rest of the
smp-bringup like reset control and entry address handling stays the same.
Its bigger sibling, the quad-core rk3128 again allows powerdomain control.

So allow that case by introducing a separate smp-enable-method, that simply
disables powerdomain handling in the common code.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NXing Zheng <zhengxing@rock-chips.com>
Acked-by: NRob Herring <robh@kernel.org>

This commit add new cpu enable method "mediatek,mt65xx-smp" and
"mediatek,mt81xx-tz-smp".
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NYingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: NMatthias Brugger <matthias.bgg@gmail.com>

The "cpus" node cannot be inside the "soc" node, while this
works for the CoreSight blocks, the early boot code will look
for "cpus" directly under the root node, so this is a hard
convention. So move the CPU nodes.

Augment the "reg" property to match what is actually in the
hardware: 0x300 and 0x301 respectively.

Then add an SMP enablement type to be used by the SMP init
code, "ste,dbx500-smp".
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The A23 is a dual Cortex-A7. Add the logic to use the IPs used to
control the CPU configuration and the CPU power so that we can
bring up secondary CPUs at boot.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

This commit updates the ARM CPUs Device Tree binding to document a new
enable method of Marvell Armada 39x processors.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

Add a compatible string for the NVIDIA Denver CPU to the ARM CPU DT
binding documentation file.  The primary objective here is to keep
checkpatch.pl from warning when the compatible string is used in an
SoC DT file, per:

http://marc.info/?l=linux-tegra&m=142201349727836&w=2

This second version changes the string from "nvidia,denver" to
"nvidia,tegra132-denver" to more precisely describe the revision of
the Denver CPU complex that is present in the Tegra132 SoC.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Olof Johansson <olof@lixom.net>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Rohit Vaswani <rvaswani@codeaurora.org>
Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Marc Carino <marc.ceeeee@gmail.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: NRob Herring <robh@kernel.org>

Makes it possible to define a rockchip,pmu phandle in the cpus node directly
referencing the pmu syscon instead of searching for specific compatible.

The old way of finding the pmu stays of course available.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Tested-by: NKevin Hilman <khilman@linaro.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This patch adds documentation for the devicetree bindings used by the
DT files of Cavium Thunder SoC platforms.
Signed-off-by: NRadha Mohan Chintakuntla <rchintakuntla@cavium.com>
Signed-off-by: NRobert Richter <rrichter@cavium.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

ARM based platforms implement a variety of power management schemes that
allow processors to enter idle states at run-time.
The parameters defining these idle states vary on a per-platform basis forcing
the OS to hardcode the state parameters in platform specific static tables
whose size grows as the number of platforms supported in the kernel increases
and hampers device drivers standardization.

Therefore, this patch aims at standardizing idle state device tree bindings
for ARM platforms. Bindings define idle state parameters inclusive of entry
methods and state latencies, to allow operating systems to retrieve the
configuration entries from the device tree and initialize the related power
management drivers, paving the way for common code in the kernel to deal with
idle states and removing the need for static data in current and previous
kernel versions.

ARM64 platforms require the DT to define an entry-method property
for idle states.

On system implementing PSCI as an enable-method to enter low-power
states the PSCI CPU suspend method requires the power_state parameter to
be passed to the PSCI CPU suspend function.

This parameter is specific to a power state and platform specific,
therefore must be provided by firmware to the OS in order to enable
proper call sequence.

Thus, this patch also adds a property in the PSCI bindings that
describes how the PSCI CPU suspend power_state parameter should be
defined in DT in all device nodes that rely on PSCI CPU suspend method usage.
Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NNicolas Pitre <nico@linaro.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Reviewed-by: NSebastian Capella <sebcape@gmail.com>
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>

Add the Broadcom Brahma B15 CPU to the DT CPU binding list.
Signed-off-by: NMarc Carino <marc.ceeeee@gmail.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NMatt Porter <mporter@linaro.org>

As announced parts from ARM they will probably be used in socs shortly.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NMark Rutland <mark.rutland@arm.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

People have appended new entries instead of inserting them at
the right location, so sort them.
Signed-off-by: NOlof Johansson <olof@lixom.net>

With the newly introduced CPU_METHOD_OF_DECLARE is not necessary anymore
to reference the relevant smp_ops in the board file, but instead it can
simply be set by the enable-method property of the cpu nodes.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Document the necently introduced A31 enable-method as a valid option.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

arm,psci is also a valid enable-method for the CPUs on ARM. Document it.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

This commit adds the SMP support for Armada 375 and Armada 38x. It
turns out that the SMP logic for both of these SOCs are fairly
similar, the only differences being:

 * A different method to set the secondary CPU boot address

 * An Armada 375 specific workaround needed for the early Z1 stepping,
   added by the following patch.

Other than that, the patch is fairly straightforward and adds the
usual platsmp and headsmp code, defining the smp_operations structure
that is referenced from the DT_MACHINE structures.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-9-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-9-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

This commit adds the CPU_METHOD_OF_DECLARE declaration for the Armada
XP SMP operations. Note that the .smp_ops field of Armada XP
DT_MACHINE structure is kept, in order to ensure we remain compatible
with older Device Trees that do not include the "enable-method"
property for the CPUs.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-3-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Scorpion and Krait don't use the spin-table enable-method.
Instead they rely on mmio register accesses to enable power and
clocks to bring CPUs out of reset. Document their enable-methods.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: NRohit Vaswani <rvaswani@codeaurora.org>
[sboyd: Split off into separate patch, renamed methods to
match compatible nodes]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NKumar Gala <galak@codeaurora.org>

In order to extend the current cpu nodes bindings to newer CPUs
inclusive of AArch64 and to update support for older ARM CPUs this
patch updates device tree documentation for the cpu nodes bindings.

Main changes:
    - adds 64-bit bindings
    - define usage of #address-cells
    - defines behaviour on pre and post v7 uniprocessor systems
    - adds ARM 11MPcore specific reg property definition
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: NMark Rutland <mark.rutland@arm.com>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: NJason Cooper <jason@lakedaemon.net>
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

When booting through a device tree, the kernel cpu logical id map can be
initialized using device tree data passed by FW or through an embedded blob.

This patch adds a function that parses device tree "cpu" nodes and
retrieves the corresponding CPUs hardware identifiers (MPIDR).
It sets the possible cpus and the cpu logical map values according to
the number of CPUs defined in the device tree and respective properties.

The device tree HW identifiers are considered valid if all CPU nodes contain
a "reg" property, there are no duplicate "reg" entries and the DT defines a
CPU node whose "reg" property matches the MPIDR[23:0] of the boot CPU.

The primary CPU is assigned cpu logical number 0 to keep the current convention
valid.

Current bindings documentation is included in the patch:

Documentation/devicetree/bindings/arm/cpus.txt
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: NNicolas Pitre <nico@linaro.org>