This adds support for the LIS331DL sensor version. This is
a simple 8bit-only accelerometer.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NDenis Ciocca <denis.ciocca@st.com>
Signed-off-by: NJonathan Cameron <jic23@kernel.org>

Support configurable conversion mode through sysfs. So far, the
mode used was low-power, which is enabled by default now. Beside
that, the modes normal and high-speed are selectable as well.

Use the new device tree property which specifies the maximum ADC
conversion clock frequencies. Depending on the mode used, the
available resulting conversion frequency are calculated
dynamically.
Acked-by: NFugang Duan <B38611@freescale.com>
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NJonathan Cameron <jic23@kernel.org>

Signed-off-by: NUrs Fässler <urs.fassler@bytesatwork.ch>
Signed-off-by: NJonathan Cameron <jic23@kernel.org>

Following the addition of a Berlin ADC driver, this patch adds the
corresponding bindings documentation.
Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: NJonathan Cameron <jic23@kernel.org>
Signed-off-by: NJonathan Cameron <jic23@kernel.org>

Add optional DT properties to set open delay, sample delay and number
of averages per sample for each adc step. Open delay, sample delay
and averaging are some of the parameters that affect the sampling rate
and accuracy of the sample. Making these parameters configurable via
DT will help in balancing speed vs accuracy.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Signed-off-by: NJonathan Cameron <jic23@kernel.org>

Signed-off-by: NVarka Bhadram <varkab@cdac.in>
Signed-off-by: NJonathan Cameron <jic23@kernel.org>

Add binding documentation for Bosch BMC150 magnetometer.
Signed-off-by: NIrina Tirdea <irina.tirdea@intel.com>
Signed-off-by: NJonathan Cameron <jic23@kernel.org>

The LSM303DLH accelerometer/magnetometer has a different
device identification method than using register 0x0f, instead
three registers contain a magic value. We rely on WhoAmI
to be zero for this variant.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NJonathan Cameron <jic23@kernel.org>

Document "altr,socfpga-cyclone5", "altr,socfpga-arria5", and
"altr,socfpga-arria10".
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: NRob Herring <robh@kernel.org>

The watchdog has been reworked to use the same DT node as the timer.
This change is updating the device tree doc accordingly.
Signed-off-by: NMathieu Olivari <mathieu@codeaurora.org>
Acked-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NWim Van Sebroeck <wim@iguana.be>

Signed-off-by: NVineet Gupta <vgupta@synopsys.com>

The doc refers to Documentation/devicetree/bindings/video/video-ports.txt
which does not exist. The documentation seems to be outdated and wants to
refer to Documentation/devicetree/bindings/graph.txt instead.
Signed-off-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Add a device tree binding documentation to the Real Time Clock hardware
block on the Conexant CX92755 SoC.  The CX92755 is from the Digicolor SoCs
series.  Other SoCs in that series may share the same hardware block.
Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

The rtc's status register allows to determine if a 32k crystal is
connected to keep the rtc running in low power states provided the
corresponding fuse bits were blown correctly during production.  (In case
they were not, the right frequency can be stated in the device tree.) If
there is no such crystal available force the 24 MHz XTAL clock to keep
running to retain the right date and time.  Otherwise use the crystal to
save some power.

It would be nice to only switch to the crystal when the XTAL clock is
about to be disabled and keep the crystal off when unneeded because XTAL
is always on while the chip is powered on.  But as sudden power loss isn't
detectable this is not save.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

The Synopsys stmmac fifo sizes are configurable, and need to be known
in order to configure certain controller features. This patch adds
tx-fifo-depth and rx-fifo-depth properties to the stmmac document
file.
Signed-off-by: NVince Bridgers <vbridger@opensource.altera.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

The ARM Generic Timer (AKA the architected timer, arm_arch_timer)
features a CPU register (CNTFRQ) which firmware is intended to
initialize, and non-secure software can read to determine the frequency
of the timer. On CPUs with secure state, this register cannot be written
from non-secure states.

The firmware of early SoCs featuring the timer did not correctly
initialize CNTFRQ correctly on all CPUs, requiring the frequency to be
described in DT as a workaround. This workaround is not complete however
as it is exposed to all software in a privileged non-secure mode
(including guests running under a hypervisor). The firmware and DTs for
recent SoCs have followed the example set by these early SoCs.

This patch updates the arch timer binding documentation to make it
clearer that the use of the clock-frequency property is a poor
work-around. The MMIO generic timer binding is similarly updated, though
this is less of a concern as there is generally no need to expose the
MMIO timers to guest OSs.
Signed-off-by: NMark Rutland <mark.rutland@arm.com>
Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Acked-by: NOlof Johansson <olof@lixom.net>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: NRob Herring <robh@kernel.org>

These apply to newly converted drivers, like serial8250/libahci/...
The examples were adapted from the regmap bindings document.
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Reviewed-by: NPeter Hurley <peter@hurleysoftware.com>
Acked-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: NRob Herring <robh@kernel.org>

Signed-off-by: NAlessio Igor Bogani <alessio.bogani@elettra.eu>
Signed-off-by: NRob Herring <robh@kernel.org>

Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>

Some board designers, when running out of clock output pads, decide to
(mis)use PWM output pads to provide a clock to external components.
This driver supports this practice by providing an adapter between the
PWM and clock bindings in the device tree. As the PWM bindings specify
the period in the device tree, this is a fixed clock.
Tested-by: NJanusz Uzycki <j.uzycki@elproma.com.pl>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

 The CRG11 clock controller is managed by remote f/w.
This driver simply maps Linux CLK ops onto mailbox api.
Signed-off-by: NAndy Green <andy.green@linaro.org>
Signed-off-by: NVincent Yang <vincent.yang@socionext.com>
Signed-off-by: NTetsuya Nuriya <nuriya.tetsuya@socionext.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Add an I2C bus driver i2c-xlp9xx.c to support the I2C block in the
XLP9xx/XLP5xx MIPS SoC. Update Kconfig and Makefile to add the
CONFIG_I2C_XLP9XX option.
Signed-off-by: NSubhendu Sekhar Behera <sbehera@broadcom.com>
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Reviewed-by: NRay Jui <rjui@broadcom.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Add vendor name "netlogic" in vendor-prefixes.txt, which will be used for
the Netlogic XLP and XLPII MIPS SoCs. These processors were from NetLogic
Microsystems that is now a part of Broadcom Corporation.
Signed-off-by: NSubhendu Sekhar Behera <sbehera@broadcom.com>
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Having a board where the I2C bus locks up occasionally made it clear
that the bus recovery in the i2c-davinci driver will only work on
some boards, because on regular boards, this will only toggle GPIO
lines that aren't muxed to the actual pins.

The I2C controller on SoCs like da850 (and da830), Keystone 2 has the
built-in capability to bit-bang its lines by using the ICPFUNC registers
of the i2c controller.
Implement the suggested procedure by toggling SCL and checking SDA using
the ICPFUNC registers of the I2C controller when present. Allow platforms
to indicate the presence of the ICPFUNC registers with a has_pfunc platform
data flag and add optional DT property "ti,has-pfunc" to indicate
the same in DT.
Reviewed-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: NAlexander Sverdlin <alexander.sverdlin@nokia.com>
Tested-by: NMichael Lawnick <michael.lawnick@nokia.com>
Signed-off-by: NBen Gardiner <bengardiner@nanometrics.ca>
Signed-off-by: NMike Looijmans <milo-software@users.sourceforge.net>
[grygorii.strashko@ti.com: combined patches from Ben Gardiner and
Mike Looijmans and reimplemented ICPFUNC bus recovery using I2C
bus recovery infrastructure]
Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

This patch updates the binding information to reflect the
extra dt options which are now supported by the sdhci-st.c
driver which enable support for stih407 family silicon.

STiH410 SoC and later support UHS modes for eMMC, so the
driver now makes use of these common bindings. Examples
are provided for both eMMC (which has additional bindings)
and also sd slot for STiH407.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Acked-by: NMaxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Add support for system sleep and runtime power management.

To wake up the device, the SDA line should be held low for at least 33ms
while SCL is high.  As this is not possible using the i2c API (and not
supported by all i2c adapters), a GPIO connected to the SDA line is
needed.  The GPIO is named "wakeup" and can be specified in a device
tree with the "wakeup-gpios" binding.

If the wake-up GPIO is not given, disable power management for the
device.  Entering sleep requires an SMBus byte access, hence power
management is also disabled if byte access is not supported by the
adapter.
Signed-off-by: NVianney le Clément de Saint-Marcq <vianney.leclement@essensium.com>
Cc: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
Signed-off-by: NJonathan Cameron <jic23@kernel.org>

Also introduce "melexis" as a vendor prefix for device tree bindings.
Signed-off-by: NVianney le Clément de Saint-Marcq <vianney.leclement@essensium.com>
Cc: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
Signed-off-by: NJonathan Cameron <jic23@kernel.org>

As requested by Sakari:

	"The driver changes are still being reviewed.
	 It's been proposed that the max-microamp property be renamed."

So, as the DT bindings are not agreed upstream yet, let's revert
it.
Requested-by: NSakari Ailus <sakari.ailus@iki.fi>
This reverts commit b6100f10.

Add the regulator subnodes to the Qualcomm RPM MFD device tree bindings.
Signed-off-by: NBjorn Andersson <bjorn.andersson@sonymobile.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Nokia N900 is switching to device tree, make sure we can use flash
there, too.
Signed-off-by: NPavel Machek <pavel@ucw.cz>
Signed-off-by: NMauro Carvalho Chehab <mchehab@osg.samsung.com>

When the CONTINUE bit is set, the interrupt status we are polling to
identify if a transaction has finished can be sporadic.  Even though
the transfer has finished, the interrupt status may erroneously
indicate that there is still data in the FIFO.  This behaviour causes
random timeouts in large PIO transfers.

Instead of using the CONTINUE bit to control the CS lines, use the SPI
core's CS GPIO handling.  Also, now that the CONTINUE bit is not being
used, we can poll for the ALLDONE interrupt to indicate transfer
completion.
Signed-off-by: NSifan Naeem <sifan.naeem@imgtec.com>
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@imgtec.com>
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Signed-off-by: NMark Brown <broonie@kernel.org>

Document the Broadcom iProc PCIe platform interface device tree binding.
Signed-off-by: NRay Jui <rjui@broadcom.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

The DWMAC block on certain SoCs (such as IMG Pistachio) have a second
clock which must be enabled in order to access the peripheral's
register interface, so add support for requesting and enabling an
optional "pclk".
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Cc: James Hartley <james.hartley@imgtec.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Add compatible string definitions and supported pin functions.
Signed-off-by: NIvan T. Ivanov <ivan.ivanov@linaro.org>
Acked-by: NBjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

r8a73a4 is R-Mobile APE6, not AP6.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NEduardo Valentin <edubezval@gmail.com>

Currently the "function" + "groups" combination is the only documented
format for pinmux nodes, although many drivers use "function" + "pins".
Update the generic pinctrl binding to include the "function" + "pins"
combination as well.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NCharles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

JPEG IP found in Exynos5420 is similar to what is in Exynos3250, but
there are some subtle differences which this patch takes into account.
Signed-off-by: NAndrzej Pietrasiewicz <andrzej.p@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NMauro Carvalho Chehab <mchehab@osg.samsung.com>

Add the compatible string for Meson8b in Meson pinctrl documentation
and add new information for Meson8b in source code comments.
Signed-off-by: NCarlo Caione <carlo@endlessm.com>
Acked-by: NBeniamino Galvani <b.galvani@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

According to description in 'include/net/dsa.h', in cascade switches
configurations where there are more than one interconnected devices,
'rtable' array in 'dsa_chip_data' structure is used to indicate which
port on this switch should be used to send packets to that are destined
for corresponding switch.

However, dsa_of_setup_routing_table() fills 'rtable' with port numbers
of the _target_ switch, but not current one.

This commit removes redundant devicetree parsing and adds needed port
number as a function argument. So dsa_of_setup_routing_table() now just
looks for target switch number by parsing parent of 'link' device node.

To remove possible misunderstandings with the way of determining target
switch number, a corresponding comment was added to the source code and
to the DSA device tree bindings documentation file.

This was tested on a custom board with two Marvell 88E6095 switches with
following corresponding routing tables: { -1, 10 } and { 8, -1 }.
Signed-off-by: NPavel Nakonechny <pavel.nakonechny@skitlab.ru>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>