1. 23 10月, 2008 1 次提交
  2. 23 7月, 2008 1 次提交
    • V
      x86: consolidate header guards · 77ef50a5
      Vegard Nossum 提交于
      This patch is the result of an automatic script that consolidates the
      format of all the headers in include/asm-x86/.
      
      The format:
      
      1. No leading underscore. Names with leading underscores are reserved.
      2. Pathname components are separated by two underscores. So we can
         distinguish between mm_types.h and mm/types.h.
      3. Everything except letters and numbers are turned into single
         underscores.
      Signed-off-by: NVegard Nossum <vegard.nossum@gmail.com>
      77ef50a5
  3. 11 10月, 2007 1 次提交
  4. 22 7月, 2007 2 次提交
  5. 22 5月, 2007 1 次提交
    • A
      Detach sched.h from mm.h · e8edc6e0
      Alexey Dobriyan 提交于
      First thing mm.h does is including sched.h solely for can_do_mlock() inline
      function which has "current" dereference inside. By dealing with can_do_mlock()
      mm.h can be detached from sched.h which is good. See below, why.
      
      This patch
      a) removes unconditional inclusion of sched.h from mm.h
      b) makes can_do_mlock() normal function in mm/mlock.c
      c) exports can_do_mlock() to not break compilation
      d) adds sched.h inclusions back to files that were getting it indirectly.
      e) adds less bloated headers to some files (asm/signal.h, jiffies.h) that were
         getting them indirectly
      
      Net result is:
      a) mm.h users would get less code to open, read, preprocess, parse, ... if
         they don't need sched.h
      b) sched.h stops being dependency for significant number of files:
         on x86_64 allmodconfig touching sched.h results in recompile of 4083 files,
         after patch it's only 3744 (-8.3%).
      
      Cross-compile tested on
      
      	all arm defconfigs, all mips defconfigs, all powerpc defconfigs,
      	alpha alpha-up
      	arm
      	i386 i386-up i386-defconfig i386-allnoconfig
      	ia64 ia64-up
      	m68k
      	mips
      	parisc parisc-up
      	powerpc powerpc-up
      	s390 s390-up
      	sparc sparc-up
      	sparc64 sparc64-up
      	um-x86_64
      	x86_64 x86_64-up x86_64-defconfig x86_64-allnoconfig
      
      as well as my two usual configs.
      Signed-off-by: NAlexey Dobriyan <adobriyan@gmail.com>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      e8edc6e0
  6. 07 12月, 2006 1 次提交
  7. 26 9月, 2006 2 次提交
  8. 30 7月, 2006 1 次提交
    • J
      [PATCH] x86_64: Calgary IOMMU - Multi-Node NULL pointer dereference fix · d2105b10
      Jon Mason 提交于
      Calgary hits a NULL pointer dereference when booting in a multi-chassis
      NUMA system.  See Redhat bugzilla number 198498, found by Konrad
      Rzeszutek (konradr@redhat.com).
      
      There are many issues that had to be resolved to fix this problem.
      Firstly when I originally wrote the code to handle NUMA systems, I
      had a large misunderstanding that was not corrected until now.  That was
      that I thought the "number of nodes online" referred to number of
      physical systems connected.  So that if NUMA was disabled, there
      would only be 1 node and it would only show that node's PCI bus.
      In reality if NUMA is disabled, the system displays all of the
      connected chassis as one node but is only ignorant of the delays
      in accessing main memory.  Therefore, references to num_online_nodes()
      and MAX_NUMNODES are incorrect and need to be set to the maximum
      number of nodes that can be accessed (which are 8).  I created a
      variable, MAX_NUM_CHASSIS, and set it to 8 to fix this.
      
      Secondly, when walking the PCI in detect_calgary, the code only
      checked the first "slot" when looking to see if a device is present.
      This will work for most cases, but unfortunately it isn't always the
      case.  In the NUMA MXE drawers, there are USB devices present on the
      3rd slot (with slot 1 being empty).  So, to work around this, all
      slots (up to 8) are scanned to see if there are any devices present.
      
      Lastly, the bus is being enumerated on large systems in a different
      way the we originally thought.  This throws the ugly logic we had
      out the window.  To more elegantly handle this, I reorganized the
      kva array to be sparse (which removed the need to have any bus number
      to kva slot logic in tce.c) and created a secondary space array to
      contain the bus number to phb mapping.
      
      With these changes Calgary boots on an x460 with 4 nodes with and
      without NUMA enabled.
      Signed-off-by: NJon Mason <jdmason@us.ibm.com>
      Signed-off-by: NMuli Ben-Yehuda <muli@il.ibm.com>
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      d2105b10
  9. 11 7月, 2006 1 次提交
  10. 27 6月, 2006 1 次提交
    • J
      [PATCH] x86_64: Calgary IOMMU - Calgary specific bits · e465058d
      Jon Mason 提交于
      This patch hooks Calgary into the build, the x86-64 IOMMU
      initialization paths, and introduces the Calgary specific bits.  The
      implementation draws inspiration from both PPC (which has support for
      the same chip but requires firmware support which we don't have on
      x86-64) and gart. Calgary is different from gart in that it support a
      translation table per PHB, as opposed to the single gart aperture.
      
      Changes from previous version:
       * Addition of boot-time disablement for bus-level translation/isolation
         (e.g, enable userspace DMA for things like X)
       * Usage of newer IOMMU abstraction functions
      Signed-off-by: NMuli Ben-Yehuda <muli@il.ibm.com>
      Signed-off-by: NJon Mason <jdmason@us.ibm.com>
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      e465058d