1. 29 11月, 2016 1 次提交
  2. 08 10月, 2016 1 次提交
    • V
      atomic64: no need for CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE · 51a02124
      Vineet Gupta 提交于
      This came to light when implementing native 64-bit atomics for ARCv2.
      
      The atomic64 self-test code uses CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
      to check whether atomic64_dec_if_positive() is available.  It seems it
      was needed when not every arch defined it.  However as of current code
      the Kconfig option seems needless
      
       - for CONFIG_GENERIC_ATOMIC64 it is auto-enabled in lib/Kconfig and a
         generic definition of API is present lib/atomic64.c
       - arches with native 64-bit atomics select it in arch/*/Kconfig and
         define the API in their headers
      
      So I see no point in keeping the Kconfig option
      
      Compile tested for:
       - blackfin (CONFIG_GENERIC_ATOMIC64)
       - x86 (!CONFIG_GENERIC_ATOMIC64)
       - ia64
      
      Link: http://lkml.kernel.org/r/1473703083-8625-3-git-send-email-vgupta@synopsys.comSigned-off-by: NVineet Gupta <vgupta@synopsys.com>
      Cc: Richard Henderson <rth@twiddle.net>
      Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
      Cc: Matt Turner <mattst88@gmail.com>
      Cc: Russell King <linux@armlinux.org.uk>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: "James E.J. Bottomley" <jejb@parisc-linux.org>
      Cc: Helge Deller <deller@gmx.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Michael Ellerman <mpe@ellerman.id.au>
      Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
      Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
      Cc: "David S. Miller" <davem@davemloft.net>
      Cc: Chris Metcalf <cmetcalf@mellanox.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Cc: Vineet Gupta <vgupta@synopsys.com>
      Cc: Zhaoxiu Zeng <zhaoxiu.zeng@gmail.com>
      Cc: Linus Walleij <linus.walleij@linaro.org>
      Cc: Alexander Potapenko <glider@google.com>
      Cc: Andrey Ryabinin <aryabinin@virtuozzo.com>
      Cc: Herbert Xu <herbert@gondor.apana.org.au>
      Cc: Ming Lin <ming.l@ssi.samsung.com>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Geert Uytterhoeven <geert@linux-m68k.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Borislav Petkov <bp@suse.de>
      Cc: Andi Kleen <ak@linux.intel.com>
      Cc: Boqun Feng <boqun.feng@gmail.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      51a02124
  3. 24 9月, 2016 1 次提交
  4. 22 9月, 2016 1 次提交
  5. 21 9月, 2016 1 次提交
  6. 16 8月, 2016 1 次提交
    • L
      ARM: realview: imply device tree boot · 8f2c0062
      Linus Walleij 提交于
      This reduces the Kconfig for the RealView by assuming we are
      always booting from the device tree, and removing all the uses
      of CONFIG_REALVIEW_DT and replacing with CONFIG_ARCH_REALVIEW.
      
      Further:
      
      - Drop REALVIEW_HIGH_PHYS_OFFSET: we don't use this with device
        tree.
      
      - Drop the REALVIEW_EB_ARM11MP_REVB option: we now handle this
        by simply using another device tree.
      
      - Drop the PB1176 secure flash option: this is defined in the
        PB1176 device tree but marked as "disabled", so users who
        want to use it can simply enable it in the device tree and
        go hacking around.
      
      Cc: Brian Norris <computersforpeace@gmail.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      8f2c0062
  7. 27 7月, 2016 1 次提交
  8. 21 7月, 2016 1 次提交
  9. 14 7月, 2016 3 次提交
    • D
      ARM: 8560/1: errata: Workaround errata A12 825619 / A17 852421 · 9f6f9354
      Doug Anderson 提交于
      The workaround for both errata is to set bit 24 in the diagnostic
      register.  There are no known end-user bugs solved by fixing this
      errata, but the fix is trivial and it seems sane to apply it.
      
      The arguments for why this needs to be in the kernel are similar to the
      arugments made in the patch "Workaround errata A12 818325/852422 A17
      852423".
      Signed-off-by: NDouglas Anderson <dianders@chromium.org>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      9f6f9354
    • D
      ARM: 8559/1: errata: Workaround erratum A12 821420 · 416bcf21
      Doug Anderson 提交于
      This erratum has a very simple workaround (set a bit in a register), so
      let's apply it.  Apparently the workaround's downside is a very slight
      power impact.
      
      Note that applying this errata fixes deadlocks that are easy to
      reproduce with real world applications.
      
      The arguments for why this needs to be in the kernel are similar to the
      arugments made in the patch "Workaround errata A12 818325/852422 A17
      852423".
      Signed-off-by: NDouglas Anderson <dianders@chromium.org>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      416bcf21
    • D
      ARM: 8558/1: errata: Workaround errata A12 818325/852422 A17 852423 · 62c0f4a5
      Doug Anderson 提交于
      There are several similar errata on Cortex A12 and A17 that all have the same workaround: setting bit[12] of the Feature Register.
      Technically the list of errata are:
      
      - A12 818325: Execution of an UNPREDICTABLE STR or STM instruction
        might deadlock.  Fixed in r0p1.
      - A12 852422: Execution of a sequence of instructions might lead to
        either a data corruption or a CPU deadlock.  Not fixed in any A12s
        yet.
      - A17 852423: Execution of a sequence of instructions might lead to
        either a data corruption or a CPU deadlock.  Not fixed in any A17s
        yet.
      
      Since A12 got renamed to A17 it seems likely that there won't be any
      future Cortex-A12 cores, so we'll enable for all Cortex-A12.
      
      For Cortex-A17 I believe that all known revisions are affected and that all knows revisions means <= r1p2.  Presumably if a new A17 was
      released it would have this problem fixed.
      
      Note that in <https://patchwork.kernel.org/patch/4735341/> folks
      previously expressed opposition to this change because:
      A) It was thought to only apply to r0p0 and there were no known r0p0
         boards supported in mainline.
      B) It was argued that such a workaround beloned in firmware.
      
      Now that this same fix solves other errata on real boards (like
      rk3288) point A) is addressed.
      
      Point B) is impossible to address on boards like rk3288.  On rk3288
      the firmware doesn't stay resident in RAM and isn't involved at all in
      the suspend/resume process nor in the SMP bringup process.  That means
      that the most the firmware could do would be to set the bit on "core
      0" and this bit would be lost at suspend/resume time.  It is true that
      we could write a "generic" solution that saved the boot-time "core 0"
      value of this register and applied it at SMP bringup / resume time.
      However, since this register (described as the "Feature Register" in
      errata) appears to be undocumented (as far as I can tell) and is only
      modified for these errata, that "generic" solution seems questionably
      cleaner.  The generic solution also won't fix existing users that
      haven't happened to do a FW update.
      
      Note that in ARM64 presumably PSCI will be universal and fixes like
      this will end up in ATF.  Hopefully we are nearing the end of this
      style of errata workaround.
      Signed-off-by: NDouglas Anderson <dianders@chromium.org>
      Signed-off-by: NHuang Tao <huangtao@rock-chips.com>
      Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      62c0f4a5
  10. 06 7月, 2016 1 次提交
  11. 28 6月, 2016 1 次提交
  12. 16 6月, 2016 1 次提交
    • A
      PCI/MSI: irqchip: Fix PCI_MSI dependencies · 3ee80364
      Arnd Bergmann 提交于
      The PCI_MSI symbol is used inconsistently throughout the tree, with some
      drivers using 'select' and others using 'depends on', or using conditional
      selects.  This keeps causing problems; the latest one is a result of
      ARCH_ALPINE using a 'select' statement to enable its platform-specific MSI
      driver without enabling MSI:
      
        warning: (ARCH_ALPINE) selects ALPINE_MSI which has unmet direct dependencies (PCI && PCI_MSI)
        drivers/irqchip/irq-alpine-msi.c:104:15: error: variable 'alpine_msix_domain_info' has initializer but incomplete type
         static struct msi_domain_info alpine_msix_domain_info = {
      		 ^~~~~~~~~~~~~~~
        drivers/irqchip/irq-alpine-msi.c:105:2: error: unknown field 'flags' specified in initializer
          .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
          ^
        drivers/irqchip/irq-alpine-msi.c:105:11: error: 'MSI_FLAG_USE_DEF_DOM_OPS' undeclared here (not in a function)
          .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
      	     ^~~~~~~~~~~~~~~~~~~~~~~~
      
      There is little reason to enable PCI support for a platform that uses MSI
      but then leave MSI disabled at compile time.
      
      Select PCI_MSI from irqchips that implement MSI, and make PCI host bridges
      that use MSI on ARM depend on PCI_MSI_IRQ_DOMAIN.
      
      For all three architectures that support PCI_MSI_IRQ_DOMAIN (ARM, ARM64,
      X86), enable it by default whenever MSI is enabled.
      
      [bhelgaas: changelog, omit crypto config change]
      Suggested-by: NMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
      3ee80364
  13. 08 6月, 2016 1 次提交
    • E
      GCC plugin infrastructure · 6b90bd4b
      Emese Revfy 提交于
      This patch allows to build the whole kernel with GCC plugins. It was ported from
      grsecurity/PaX. The infrastructure supports building out-of-tree modules and
      building in a separate directory. Cross-compilation is supported too.
      Currently the x86, arm, arm64 and uml architectures enable plugins.
      
      The directory of the gcc plugins is scripts/gcc-plugins. You can use a file or a directory
      there. The plugins compile with these options:
       * -fno-rtti: gcc is compiled with this option so the plugins must use it too
       * -fno-exceptions: this is inherited from gcc too
       * -fasynchronous-unwind-tables: this is inherited from gcc too
       * -ggdb: it is useful for debugging a plugin (better backtrace on internal
          errors)
       * -Wno-narrowing: to suppress warnings from gcc headers (ipa-utils.h)
       * -Wno-unused-variable: to suppress warnings from gcc headers (gcc_version
          variable, plugin-version.h)
      
      The infrastructure introduces a new Makefile target called gcc-plugins. It
      supports all gcc versions from 4.5 to 6.0. The scripts/gcc-plugin.sh script
      chooses the proper host compiler (gcc-4.7 can be built by either gcc or g++).
      This script also checks the availability of the included headers in
      scripts/gcc-plugins/gcc-common.h.
      
      The gcc-common.h header contains frequently included headers for GCC plugins
      and it has a compatibility layer for the supported gcc versions.
      
      The gcc-generate-*-pass.h headers automatically generate the registration
      structures for GIMPLE, SIMPLE_IPA, IPA and RTL passes.
      
      Note that 'make clean' keeps the *.so files (only the distclean or mrproper
      targets clean all) because they are needed for out-of-tree modules.
      
      Based on work created by the PaX Team.
      Signed-off-by: NEmese Revfy <re.emese@gmail.com>
      Acked-by: NKees Cook <keescook@chromium.org>
      Signed-off-by: NMichal Marek <mmarek@suse.com>
      6b90bd4b
  14. 04 6月, 2016 1 次提交
    • L
      ARM: do away with ARCH_[WANT_OPTIONAL|REQUIRE]_GPIOLIB · 5c34a4e8
      Linus Walleij 提交于
      This replaces:
      
      - "select ARCH_REQUIRE_GPIOLIB" with "select GPIOLIB" as this can
        now be selected directly.
      
      - "select ARCH_WANT_OPTIONAL_GPIOLIB" with no dependency: GPIOLIB
        is now selectable by everyone, so we need not declare our
        intent to select it.
      
      When ordering the symbols the following rationale was used:
      if the selects were in alphabetical order, I moved select GPIOLIB
      to be in alphabetical order, but if the selects were not
      maintained in alphabetical order, I just replaced
      "select ARCH_REQUIRE_GPIOLIB" with "select GPIOLIB".
      
      Cc: Michael Büsch <m@bues.ch>
      Cc: arm@kernel.org
      Cc: linux-arm-kernel@lists.infradead.org
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      5c34a4e8
  15. 21 5月, 2016 2 次提交
    • P
      printk/nmi: generic solution for safe printk in NMI · 42a0bb3f
      Petr Mladek 提交于
      printk() takes some locks and could not be used a safe way in NMI
      context.
      
      The chance of a deadlock is real especially when printing stacks from
      all CPUs.  This particular problem has been addressed on x86 by the
      commit a9edc880 ("x86/nmi: Perform a safe NMI stack trace on all
      CPUs").
      
      The patchset brings two big advantages.  First, it makes the NMI
      backtraces safe on all architectures for free.  Second, it makes all NMI
      messages almost safe on all architectures (the temporary buffer is
      limited.  We still should keep the number of messages in NMI context at
      minimum).
      
      Note that there already are several messages printed in NMI context:
      WARN_ON(in_nmi()), BUG_ON(in_nmi()), anything being printed out from MCE
      handlers.  These are not easy to avoid.
      
      This patch reuses most of the code and makes it generic.  It is useful
      for all messages and architectures that support NMI.
      
      The alternative printk_func is set when entering and is reseted when
      leaving NMI context.  It queues IRQ work to copy the messages into the
      main ring buffer in a safe context.
      
      __printk_nmi_flush() copies all available messages and reset the buffer.
      Then we could use a simple cmpxchg operations to get synchronized with
      writers.  There is also used a spinlock to get synchronized with other
      flushers.
      
      We do not longer use seq_buf because it depends on external lock.  It
      would be hard to make all supported operations safe for a lockless use.
      It would be confusing and error prone to make only some operations safe.
      
      The code is put into separate printk/nmi.c as suggested by Steven
      Rostedt.  It needs a per-CPU buffer and is compiled only on
      architectures that call nmi_enter().  This is achieved by the new
      HAVE_NMI Kconfig flag.
      
      The are MN10300 and Xtensa architectures.  We need to clean up NMI
      handling there first.  Let's do it separately.
      
      The patch is heavily based on the draft from Peter Zijlstra, see
      
        https://lkml.org/lkml/2015/6/10/327
      
      [arnd@arndb.de: printk-nmi: use %zu format string for size_t]
      [akpm@linux-foundation.org: min_t->min - all types are size_t here]
      Signed-off-by: NPetr Mladek <pmladek@suse.com>
      Suggested-by: NPeter Zijlstra <peterz@infradead.org>
      Suggested-by: NSteven Rostedt <rostedt@goodmis.org>
      Cc: Jan Kara <jack@suse.cz>
      Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>	[arm part]
      Cc: Daniel Thompson <daniel.thompson@linaro.org>
      Cc: Jiri Kosina <jkosina@suse.com>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
      Cc: David Miller <davem@davemloft.net>
      Cc: Daniel Thompson <daniel.thompson@linaro.org>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      42a0bb3f
    • J
      exit_thread: remove empty bodies · 5f56a5df
      Jiri Slaby 提交于
      Define HAVE_EXIT_THREAD for archs which want to do something in
      exit_thread. For others, let's define exit_thread as an empty inline.
      
      This is a cleanup before we change the prototype of exit_thread to
      accept a task parameter.
      
      [akpm@linux-foundation.org: fix mips]
      Signed-off-by: NJiri Slaby <jslaby@suse.cz>
      Cc: "David S. Miller" <davem@davemloft.net>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Cc: "James E.J. Bottomley" <jejb@parisc-linux.org>
      Cc: Aurelien Jacquiot <a-jacquiot@ti.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Chen Liqin <liqin.linux@gmail.com>
      Cc: Chris Metcalf <cmetcalf@mellanox.com>
      Cc: Chris Zankel <chris@zankel.net>
      Cc: David Howells <dhowells@redhat.com>
      Cc: Fenghua Yu <fenghua.yu@intel.com>
      Cc: Geert Uytterhoeven <geert@linux-m68k.org>
      Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
      Cc: Haavard Skinnemoen <hskinnemoen@gmail.com>
      Cc: Hans-Christian Egtvedt <egtvedt@samfundet.no>
      Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
      Cc: Helge Deller <deller@gmx.de>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: Jeff Dike <jdike@addtoit.com>
      Cc: Jesper Nilsson <jesper.nilsson@axis.com>
      Cc: Jiri Slaby <jslaby@suse.cz>
      Cc: Jonas Bonn <jonas@southpole.se>
      Cc: Koichi Yasutake <yasutake.koichi@jp.panasonic.com>
      Cc: Lennox Wu <lennox.wu@gmail.com>
      Cc: Ley Foon Tan <lftan@altera.com>
      Cc: Mark Salter <msalter@redhat.com>
      Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
      Cc: Matt Turner <mattst88@gmail.com>
      Cc: Max Filippov <jcmvbkbc@gmail.com>
      Cc: Michael Ellerman <mpe@ellerman.id.au>
      Cc: Michal Simek <monstr@monstr.eu>
      Cc: Mikael Starvik <starvik@axis.com>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Rich Felker <dalias@libc.org>
      Cc: Richard Henderson <rth@twiddle.net>
      Cc: Richard Kuo <rkuo@codeaurora.org>
      Cc: Richard Weinberger <richard@nod.at>
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Steven Miao <realmz6@gmail.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Tony Luck <tony.luck@intel.com>
      Cc: Vineet Gupta <vgupta@synopsys.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      5f56a5df
  16. 17 5月, 2016 1 次提交
    • D
      bpf: split HAVE_BPF_JIT into cBPF and eBPF variant · 6077776b
      Daniel Borkmann 提交于
      Split the HAVE_BPF_JIT into two for distinguishing cBPF and eBPF JITs.
      
      Current cBPF ones:
      
        # git grep -n HAVE_CBPF_JIT arch/
        arch/arm/Kconfig:44:    select HAVE_CBPF_JIT
        arch/mips/Kconfig:18:   select HAVE_CBPF_JIT if !CPU_MICROMIPS
        arch/powerpc/Kconfig:129:       select HAVE_CBPF_JIT
        arch/sparc/Kconfig:35:  select HAVE_CBPF_JIT
      
      Current eBPF ones:
      
        # git grep -n HAVE_EBPF_JIT arch/
        arch/arm64/Kconfig:61:  select HAVE_EBPF_JIT
        arch/s390/Kconfig:126:  select HAVE_EBPF_JIT if PACK_STACK && HAVE_MARCH_Z196_FEATURES
        arch/x86/Kconfig:94:    select HAVE_EBPF_JIT                    if X86_64
      
      Later code also needs this facility to check for eBPF JITs.
      Signed-off-by: NDaniel Borkmann <daniel@iogearbox.net>
      Acked-by: NAlexei Starovoitov <ast@kernel.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      6077776b
  17. 11 5月, 2016 1 次提交
    • V
      irqchip: Add LPC32xx interrupt controller driver · 8cb17b5e
      Vladimir Zapolskiy 提交于
      The change adds improved support of NXP LPC32xx MIC, SIC1 and SIC2
      interrupt controllers.
      
      This is a list of new features in comparison to the legacy driver:
      * irq types are taken from device tree settings, no more need to
        hardcode them,
      * old driver is based on irq_domain_add_legacy, which causes problems
        with handling MIC hardware interrupt 0 produced by SIC1,
      * there is one driver for MIC, SIC1 and SIC2, no more need to handle
        them separately, e.g. have two separate handlers for SIC1 and SIC2,
      * the driver does not have any dependencies on hardcoded register
        offsets,
      * the driver is much simpler for maintenance,
      * SPARSE_IRQS option is supported.
      
      Legacy LPC32xx interrupt controller driver was broken since commit
      76ba59f8 ("genirq: Add irq_domain-aware core IRQ handler"), which
      requires a private interrupt handler, otherwise any SIC1 generated
      interrupt (mapped to MIC hwirq 0) breaks the kernel with the message
      "unexpected IRQ trap at vector 00".
      
      The change disables compilation of a legacy driver found at
      arch/arm/mach-lpc32xx/irq.c, the file will be removed in a separate
      commit.
      
      Fixes: 76ba59f8 ("genirq: Add irq_domain-aware core IRQ handler")
      Tested-by: NSylvain Lemieux <slemieux.tyco@gmail.com>
      Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      8cb17b5e
  18. 09 5月, 2016 1 次提交
    • J
      arm: Add Aspeed machine · 8c2ed9bc
      Joel Stanley 提交于
      Aspeed devices are a common Baseboard Management Controller (BMC)
      system on chip containing an ARM9 or ARM11 core, off-chip DDR RAM and
      support for a large number of peripherals.
      
      This patch adds basic support for the ast2400 and ast2500 machines,
      capable of booting to a prompt in QEMU (-M palmetto-bmc), on an
      Palmetto OpenPower development machine, and on the ast2500 EVB.
      Signed-off-by: NJoel Stanley <joel@jms.id.au>
      8c2ed9bc
  19. 26 4月, 2016 2 次提交
  20. 09 3月, 2016 1 次提交
    • B
      PCI: Include pci/pcie/Kconfig directly from pci/Kconfig · 5f8fc432
      Bogicevic Sasa 提交于
      Include pci/pcie/Kconfig directly from pci/Kconfig, so arches don't
      have to source both pci/Kconfig and pci/pcie/Kconfig.
      
      Note that this effectively adds pci/pcie/Kconfig to the following
      arches, because they already sourced drivers/pci/Kconfig but they
      previously did not source drivers/pci/pcie/Kconfig:
      
        alpha
        avr32
        blackfin
        frv
        m32r
        m68k
        microblaze
        mn10300
        parisc
        sparc
        unicore32
        xtensa
      
      [bhelgaas: changelog, source pci/pcie/Kconfig at top of pci/Kconfig, whitespace]
      Signed-off-by: NSasa Bogicevic <brutallesale@gmail.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      5f8fc432
  21. 25 2月, 2016 1 次提交
  22. 23 2月, 2016 1 次提交
    • A
      ARM: 8530/1: remove VIRT_TO_BUS · 9e0087e6
      Arnd Bergmann 提交于
      All drivers that are relevant for rpc or footbridge have stopped
      using virt_to_bus a while ago, so we can remove it and avoid some
      harmless randconfig warnings for drivers that we do not care about:
      
      drivers/atm/zatm.c: In function 'poll_rx':
      drivers/atm/zatm.c:401:18: warning: 'bus_to_virt' is deprecated [-Wdeprecated-declarations]
         skb = ((struct rx_buffer_head *) bus_to_virt(here[2]))->skb;
      
      FWIW, the remaining drivers using this are:
      
      ATM:  firestream, zatm, ambassador, horizon
      ISDN: hisax/netjet
      V4L:  STA2X11, zoran
      Net:  Appletalk LTPC, Tulip DE4x5, Toshiba IrDA
      WAN:  comtrol sv11, cosa, lanmedia, sealevel
      SCSI: DPT_I2O, buslogic
      VME:  CA91C142
      
      My best guess is that all of the above are so hopelessly obsolete that
      we are best off removing all of them form the kernel, but that can be
      done another time.
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      9e0087e6
  23. 17 2月, 2016 1 次提交
  24. 11 2月, 2016 4 次提交
    • L
      ARM: 8511/1: ARM64: kernel: PSCI: move PSCI idle management code to drivers/firmware · 8b6f2499
      Lorenzo Pieralisi 提交于
      ARM64 PSCI kernel interfaces that initialize idle states and implement
      the suspend API to enter them are generic and can be shared with the
      ARM architecture.
      
      To achieve that goal, this patch moves ARM64 PSCI idle management
      code to drivers/firmware, so that the interface to initialize and
      enter idle states can actually be shared by ARM and ARM64 arches
      back-ends.
      
      The ARM generic CPUidle implementation also requires the definition of
      a cpuidle_ops section entry for the kernel to initialize the CPUidle
      operations at boot based on the enable-method (ie ARM64 has the
      statically initialized cpu_ops counterparts for that purpose); therefore
      this patch also adds the required section entry on CONFIG_ARM for PSCI so
      that the kernel can initialize the PSCI CPUidle back-end when PSCI is
      the probed enable-method.
      
      On ARM64 this patch provides no functional change.
      Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
      Acked-by: Catalin Marinas <catalin.marinas@arm.com> [arch/arm64]
      Acked-by: NMark Rutland <mark.rutland@arm.com>
      Tested-by: NJisheng Zhang <jszhang@marvell.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Sudeep Holla <sudeep.holla@arm.com>
      Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Jisheng Zhang <jszhang@marvell.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      8b6f2499
    • L
      ARM: 8510/1: rework ARM_CPU_SUSPEND dependencies · 1b9bdf5c
      Lorenzo Pieralisi 提交于
      The code enabled by the ARM_CPU_SUSPEND config option is used by
      kernel subsystems for purposes that go beyond system suspend so its
      config entry should be augmented to take more default options into
      account and avoid forcing its selection to prevent dependencies
      override.
      
      To achieve this goal, this patch reworks the ARM_CPU_SUSPEND config
      entry and updates its default config value (by adding the BL_SWITCHER
      option to it) and its dependencies (ARCH_SUSPEND_POSSIBLE), so that the
      symbol is still selected by default by the subsystems requiring it and
      at the same time enforcing the dependencies correctly.
      Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Cc: Nicolas Pitre <nico@fluxnic.net>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      1b9bdf5c
    • V
      arm: lpc32xx: remove selected HAVE_IDE · 1465e98a
      Vladimir Zapolskiy 提交于
      NXP LPC32xx platform does not have any controller capable for disk
      drives, selection of HAVE_IDE is not needed.
      Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>
      1465e98a
    • V
      arm: lpc32xx: switch to common clock framework · c227f127
      Vladimir Zapolskiy 提交于
      The change switches NXP LPC32xx platforms to LPC32xx clock driver
      powered by common clock framework, this obsoletes mach-lpc32xx/clock.o
      legacy clock driver and thus it is removed.
      
      Legacy timer driver mach-lpc32xx/timer.o strictly depends on legacy
      clock support, but fortunately an existing LPC32xx clock source and
      clock event driver completely replaces it, and thus it can be removed
      as well.
      
      Noticeably platform UART driver directly operates on LPC32xx source
      control block registers, remove this dependency to avoid overlapping
      with common clock framework driver, also this guarantees that UART is
      working expectedly.
      Tested-by: NSylvain Lemieux <slemieux@tycoint.com>
      Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>
      c227f127
  25. 02 2月, 2016 1 次提交
  26. 28 1月, 2016 2 次提交
  27. 21 1月, 2016 1 次提交
    • C
      dma-mapping: always provide the dma_map_ops based implementation · e1c7e324
      Christoph Hellwig 提交于
      Move the generic implementation to <linux/dma-mapping.h> now that all
      architectures support it and remove the HAVE_DMA_ATTR Kconfig symbol now
      that everyone supports them.
      
      [valentinrothberg@gmail.com: remove leftovers in Kconfig]
      Signed-off-by: NChristoph Hellwig <hch@lst.de>
      Cc: "David S. Miller" <davem@davemloft.net>
      Cc: Aurelien Jacquiot <a-jacquiot@ti.com>
      Cc: Chris Metcalf <cmetcalf@ezchip.com>
      Cc: David Howells <dhowells@redhat.com>
      Cc: Geert Uytterhoeven <geert@linux-m68k.org>
      Cc: Haavard Skinnemoen <hskinnemoen@gmail.com>
      Cc: Hans-Christian Egtvedt <egtvedt@samfundet.no>
      Cc: Helge Deller <deller@gmx.de>
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: Jesper Nilsson <jesper.nilsson@axis.com>
      Cc: Koichi Yasutake <yasutake.koichi@jp.panasonic.com>
      Cc: Ley Foon Tan <lftan@altera.com>
      Cc: Mark Salter <msalter@redhat.com>
      Cc: Mikael Starvik <starvik@axis.com>
      Cc: Steven Miao <realmz6@gmail.com>
      Cc: Vineet Gupta <vgupta@synopsys.com>
      Cc: Christian Borntraeger <borntraeger@de.ibm.com>
      Cc: Joerg Roedel <jroedel@suse.de>
      Cc: Sebastian Ott <sebott@linux.vnet.ibm.com>
      Signed-off-by: NValentin Rothberg <valentinrothberg@gmail.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      e1c7e324
  28. 17 1月, 2016 1 次提交
  29. 15 1月, 2016 1 次提交
    • D
      arm: mm: support ARCH_MMAP_RND_BITS · e0c25d95
      Daniel Cashman 提交于
      arm: arch_mmap_rnd() uses a hard-code value of 8 to generate the random
      offset for the mmap base address.  This value represents a compromise
      between increased ASLR effectiveness and avoiding address-space
      fragmentation.  Replace it with a Kconfig option, which is sensibly
      bounded, so that platform developers may choose where to place this
      compromise.  Keep 8 as the minimum acceptable value.
      
      [arnd@arndb.de: ARM: avoid ARCH_MMAP_RND_BITS for NOMMU]
      Signed-off-by: NDaniel Cashman <dcashman@google.com>
      Cc: Russell King <linux@arm.linux.org.uk>
      Acked-by: NKees Cook <keescook@chromium.org>
      Cc: Ingo Molnar <mingo@kernel.org>
      Cc: Jonathan Corbet <corbet@lwn.net>
      Cc: Don Zickus <dzickus@redhat.com>
      Cc: Eric W. Biederman <ebiederm@xmission.com>
      Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
      Cc: Josh Poimboeuf <jpoimboe@redhat.com>
      Cc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
      Cc: Naoya Horiguchi <n-horiguchi@ah.jp.nec.com>
      Cc: Andrea Arcangeli <aarcange@redhat.com>
      Cc: Mel Gorman <mgorman@suse.de>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: David Rientjes <rientjes@google.com>
      Cc: Mark Salyzyn <salyzyn@android.com>
      Cc: Jeff Vander Stoep <jeffv@google.com>
      Cc: Nick Kralevich <nnk@google.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Cc: Hector Marco-Gisbert <hecmargi@upv.es>
      Cc: Borislav Petkov <bp@suse.de>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
      Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      e0c25d95
  30. 09 1月, 2016 1 次提交
  31. 05 1月, 2016 2 次提交