Skip to content

cloud-kernel
cloud-kernel

openanolis / cloud-kernel
大约 1 年 前同步成功

通知 155
Star 36
Fork 7
cloud-kernel
cloud-kernel

体验新版 GitCode，发现更多精彩内容 >>

切换分支/标签
  1. 02 12月, 2006 19 次提交
    • I
      PCI: switch pci_{enable,disable}_device() to be nestable · bae94d02
      由 Inaky Perez-Gonzalez 提交于 
      Changes the pci_{enable,disable}_device() functions to work in a
nested basis, so that eg, three calls to enable_device() require three
calls to disable_device().

The reason for this is to simplify PCI drivers for
multi-interface/capability devices. These are devices that cram more
than one interface in a single function. A relevant example of that is
the Wireless [USB] Host Controller Interface (similar to EHCI) [see
http://www.intel.com/technology/comms/wusb/whci.htm]. 

In these kind of devices, multiple interfaces are accessed through a
single bar and IRQ line. For that, the drivers map only the smallest
area of the bar to access their register banks and use shared IRQ
handlers. 

However, because the order at which those drivers load cannot be known
ahead of time, the sequence in which the calls to pci_enable_device()
and pci_disable_device() cannot be predicted. Thus:

1. driverA     starts     pci_enable_device()
2. driverB     starts     pci_enable_device()
3. driverA     shutdown   pci_disable_device()
4. driverB     shutdown   pci_disable_device()

between steps 3 and 4, driver B would loose access to it's device,
even if it didn't intend to.

By using this modification, the device won't be disabled until all the
callers to enable() have called disable().

This is implemented by replacing 'struct pci_dev->is_enabled' from a
bitfield to an atomic use count. Each caller to enable increments it,
each caller to disable decrements it. When the count increments from 0
to 1, __pci_enable_device() is called to actually enable the
device. When it drops to zero, pci_disable_device() actually does the
disabling.

We keep the backend __pci_enable_device() for pci_default_resume() to
use and also change the sysfs method implementation, so that userspace
enabling/disabling the device doesn't disable it one time too much.
Signed-off-by: NInaky Perez-Gonzalez <inaky@linux.intel.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      bae94d02
    • A
      PCI: arch/i386/kernel/pci-dma.c: ioremap balanced with iounmap · 039d09a8
      由 Amol Lad 提交于 
      ioremap must be balanced by an iounmap and failing to do so can result
in a memory leak.

Tested (compilation only):
- using allmodconfig
- making sure the files are compiling without any warning/error due to
new changes
Signed-off-by: NAmol Lad <amol@verismonetworks.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      039d09a8
    • R
      pci/i386: style cleanups · 7edab2f0
      由 Randy Dunlap 提交于 
      Mostly CodingStyle cleanups for arch/i386/pci/i386.c:
- fit in 80 columns;
- use a #defined value instead of an inline constant;
Also change one resource_size_t (DBG) printk from %08lx to %lx since
it can be more than 32 bits (more than 8 hexits).
Signed-off-by: NRandy Dunlap <randy.dunlap@oracle.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      7edab2f0
    • M
      PCI: Block on access to temporarily unavailable pci device · 7ea7e98f
      由 Matthew Wilcox 提交于 
      The existing implementation of pci_block_user_cfg_access() was recently
criticised for providing out of date information and for returning errors
on write, which applications won't be expecting.

This reimplementation uses a global wait queue and a bit per device.
I've open-coded prepare_to_wait() / finish_wait() as I could optimise
it significantly by knowing that the pci_lock protected us at all points.

It looked a bit funny to be doing a spin_unlock_irqsave(); schedule(),
so I used spin_lock_irq() for the _user versions of pci_read_config and
pci_write_config.  Not carrying a flags pointer around made the code
much less nasty.

Attempts to block an already blocked device hit a BUG() and attempts to
unblock an already unblocked device hit a WARN().  If we need to block
access to a device from userspace, it's because it's unsafe for even
another bit of the kernel to access the device.  An attempt to block
a device for a second time means we're about to access the device to
perform some other operation, which could provoke undefined behaviour
from the device.
Signed-off-by: NMatthew Wilcox <matthew@wil.cx>
Acked-by: NAdam Belay <abelay@novell.com>
Acked-by: NAlan Cox <alan@redhat.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      7ea7e98f
    • A
      pci: fix __pci_register_driver error handling · 50bf14b3
      由 Akinobu Mita 提交于 
      __pci_register_driver() error path forgot to unwind.
driver_unregister() needs to be called when pci_create_newid_file() failed.
Signed-off-by: NAkinobu Mita <akinobu.mita@gmail.com>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      50bf14b3
    • K
      pci: clear osc support flags if no _OSC method · 0dcb2b7e
      由 Kristen Carlson Accardi 提交于 
      So it looks like pci aer code will call pci_osc_support_set to tell the
firmware about  OSC_EXT_PCI_CONFIG_SUPPORT flag.  that causes
ctrlset_buf[OSC_SUPPORT_TYPE] to evaluate to true when pciehp calls
pci_osc_control_set() is called (to attempt to use OSC to gain native
pcie control from firmware), regardless of whether or not _OSC was
actually successfully executed.  That causes this section of code:
 if (ctrlset_buf[OSC_SUPPORT_TYPE] &&
                ((global_ctrlsets & ctrlset) != ctrlset)) {
                return AE_SUPPORT;
        }
to be hit.

This patch will reset the OSC_SUPPORT_TYPE field if _OSC fails, and then
would allow pciehp to go ahead and try to run _OSC again.
Signed-off-by: NKristen Carlson Accardi <kristen.c.accardi@intel.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      0dcb2b7e
    • A
      acpiphp: fix missing acpiphp_glue_exit() · 0a9dee27
      由 Akinobu Mita 提交于 
      acpiphp_glue_exit() needs to be called to unwind when no slots found.
(It fixes data corruption when reloading acpiphp driver with no such devices)
Signed-off-by: NAkinobu Mita <akinobu.mita@gmail.com>
Signed-off-by: NKristen Carlson Accardi <kristen.c.accardi@intel.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      0a9dee27
    • A
      acpiphp: fix use of list_for_each macro · 467c442f
      由 Akinobu Mita 提交于 
      This patch fixes invalid usage of list_for_each()

list_for_each (node, &bridge_list) {
	bridge = (struct acpiphp_bridge *)node;
	...
}

This code works while the member of list node is located at the
head of struct acpiphp_bridge.
Signed-off-by: NAkinobu Mita <akinobu.mita@gmail.com>
Signed-off-by: NKristen Carlson Accardi <kristen.c.accardi@intel.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      467c442f
    • J
      Altix: Initial ACPI support - ROM shadowing. · a2302c68
      由 John Keller 提交于 
      Support a shadowed ROM when running with an ACPI capable PROM.

Define a new dev.resource flag IORESOURCE_ROM_BIOS_COPY to
describe the case of a BIOS shadowed ROM, which can then
be used to avoid pci_map_rom() making an unneeded call to
pci_enable_rom().
Signed-off-by: NJohn Keller <jpk@sgi.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      a2302c68
    • J
      Altix: SN ACPI hotplug support. · 9f581f16
      由 John Keller 提交于 
      A few minor changes to the way slot/device fixup is done.

No need to be calling sn_pci_controller_fixup(), as
a root bus cannot be hotplugged.
Signed-off-by: NJohn Keller <jpk@sgi.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      9f581f16
    • J
      Altix: Add initial ACPI IO support · 8ea6091f
      由 John Keller 提交于 
      First phase in introducing ACPI support to SN.
In this phase, when running with an ACPI capable PROM,
the DSDT will define the root busses and all SN nodes
(SGIHUB, SGITIO). An ACPI bus driver will be registered
for the node devices, with the acpi_pci_root_driver being
used for the root busses. An ACPI vendor descriptor is
now used to pass platform specific information for both
nodes and busses, eliminating the need for the current
SAL calls. Also, with ACPI support, SN fixup code is no longer
needed to initiate the PCI bus scans, as the acpi_pci_root_driver
does that.

However, to maintain backward compatibility with non-ACPI capable
PROMs, none of the current 'fixup' code can been deleted, though
much restructuring has been done. For example, the bulk of the code
in io_common.c is relocated code that is now common regardless
of what PROM is running, while io_acpi_init.c and io_init.c contain
routines specific to an ACPI or non ACPI capable PROM respectively.

A new pci bus fixup platform vector has been created to provide
a hook for invoking platform specific bus fixup from pcibios_fixup_bus().

The size of io_space[] has been increased to support systems with
large IO configurations.
Signed-off-by: NJohn Keller <jpk@sgi.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      8ea6091f
    • M
      PCI: Delete unused extern in powermac/pci.c · e08cf02f
      由 Matthew Wilcox 提交于 
      This file no longer uses pci_cache_line_size, so delete the declaration
Signed-off-by: NMatthew Wilcox <matthew@wil.cx>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: NJeff Garzik <jeff@garzik.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      e08cf02f
    • M
      PCI: Replace HAVE_ARCH_PCI_MWI with PCI_DISABLE_MWI · edb2d97e
      由 Matthew Wilcox 提交于 
      pSeries is the only architecture left using HAVE_ARCH_PCI_MWI and it's
really inappropriate for its needs.  It really wants to disable MWI
altogether.  So here are a pair of stub implementations for pci_set_mwi
and pci_clear_mwi.

Also rename pci_generic_prep_mwi to pci_set_cacheline_size since that
better reflects what it does.
Signed-off-by: NMatthew Wilcox <matthew@wil.cx>
Cc: Paul Mackerras <paulus@samba.org>
Acked-by: NJeff Garzik <jeff@garzik.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      edb2d97e
    • M
      PCI: Use pci_generic_prep_mwi on sparc64 · ebf5a248
      由 Matthew Wilcox 提交于 
      The setting of the CACHE_LINE_SIZE register in sparc64's pci
initialisation code isn't quite adequate as the device may have
incompatible requirements.  The generic code tests for this, so switch
sparc64 over to using it.

Since sparc64 has different L1 cache line size and PCI cache line size,
it would need to override the generic code like i386 and ia64 do.  We
know what the cache line size is at compile time though, so introduce a
new optional constant PCI_CACHE_LINE_BYTES.
Signed-off-by: NMatthew Wilcox <matthew@wil.cx>
Signed-off-by: NDavid Miller <davem@davemloft.net>
Acked-by: NJeff Garzik <jeff@garzik.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      ebf5a248
    • M
      PCI: Use pci_generic_prep_mwi on ia64 · 3efe2d84
      由 Matthew Wilcox 提交于 
      The pci_generic_prep_mwi() code does everything that pcibios_prep_mwi()
does on ia64.  All we need to do is be sure that pci_cache_line_size
is set appropriately, and we can delete pcibios_prep_mwi().

Using SMP_CACHE_BYTES as the default was wrong on uniprocessor machines
as it is only 8 bytes.  The default in the generic code of L1_CACHE_BYTES
is at least as good.
Signed-off-by: NMatthew Wilcox <matthew@wil.cx>
Acked-by: NJeff Garzik <jeff@garzik.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      3efe2d84
    • A
      PCI: quirks: fix the festering mess that claims to handle IDE quirks · 368c73d4
      由 Alan Cox 提交于 
      The number of permutations of crap we do is amazing and almost all of it
has the wrong effect in 2.6.

At the heart of this is the PCI SFF magic which says that compatibility
mode PCI IDE controllers use ISA IRQ routing and hard coded addresses
not the BAR values. The old quirks variously clears them, sets them,
adjusts them and then IDE ignores the result.

In order to drive all this garbage out and to do it portably we need to
handle the SFF rules directly and properly. Because we know the device
BAR 0-3 are not used in compatibility mode we load them with the values
that are implied (and indeed which many controllers actually
thoughtfully put there in this mode anyway).

This removes special cases in the IDE layer and libata which now knows
that bar 0/1/2/3 always contain the correct address. It means our
resource allocation map is accurate from boot, not "mostly accurate"
after ide is loaded, and it shoots lots of code. There is also lots more
code and magic constant knowledge to shoot once this is in and settled.

Been in my test tree for a while both with drivers/ide and with libata.
Wants some -mm shakedown in case I've missed something dumb or there are
corner cases lurking.
Signed-off-by: NAlan Cox <alan@redhat.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      368c73d4
    • S
      PCI: save/restore PCI-X state · cc692a5f
      由 Stephen Hemminger 提交于 
      Shouldn't PCI-X state be saved/restored?  No device really needs this
right now. qla24xx (fc HBA) and mthca (infiniband) don't do suspend, 
and sky2 resets its tweaks when links are brought up.
Signed-off-by: NStephen Hemminger <shemminger@osdl.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      cc692a5f
    • M
      PCI: Make some MSI-X #defines generic · e65e5fb5
      由 Michael Ellerman 提交于 
      Move some MSI-X #defines into pci_regs.h so they can be used
outside of drivers/pci.
Signed-off-by: NMichael Ellerman <michael@ellerman.id.au>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      e65e5fb5
    • G
      PCI: Let PCI_MULTITHREAD_PROBE not be broken · 009af1ff
      由 Greg Kroah-Hartman 提交于 
      It's not really broken, but people keep running into other problems
caused by it.  Re-enable it so that the drivers get stress tested.
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      009af1ff
  3. 30 11月, 2006 5 次提交
  5. 29 11月, 2006 16 次提交