Initial default tx phase was set to 0 while the datasheet recommends 270.
Some cards fails to initialize with this setting and eMMC mode DDR52 does
not work.

Changing this setting to 270 fixes these issues, without any regression
so far
Reviewed-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Implement voltage switch callback (shamelessly copied from sunxi mmc
driver). This allow, with the appropriate tuning function, to use
SD ultra high speed modes.
Reviewed-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Several phases can be controlled on the meson-gx controller, the core, tx
and rx clock phase. The tx and rx uses delays to allow  more fine grained
setting of the phase. To properly compute the phase using delays,
accessing the clock rate is necessary.

Instead of ad-hoc functions, use the common clock framework to set the
clock phases (and access the clock rate while doing it).
Acked-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Implement the card_busy callback to be able to verify that the
card is done dealing with voltage switch, when the support is
added later on.
Reviewed-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

No functional change, just improve interrupt handler readability
Reviewed-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

It seems that the mmc clock is also used and required, somehow, by
the controller itself.

It is shown during init, when writing to CFG while the divider is set
to 0 will crash the SoC. During a voltage switch, the controller may
crash and the card may then fail to exit busy state if the clock is
stopped.

To avoid this, it is best to keep the clock running for the controller,
except during rate change. However, we still need to be able to gate
the clock out of the SoC. Let's use the pinmux for this, and fallback
to gpio mode (pulled-down) when we need to gate the clock
Reviewed-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

In DDR modes, meson mmc controller requires an input rate twice as fast
as the output rate

Fixes: 51c5d844 ("MMC: meson: initial support for GX platforms")
Reviewed-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Thanks to devm, carrying the clock structure around after init is not
necessary. Rework the function to remove these from the controller host
data.

Finally, set initial mmc clock rate before enabling it, simplifying the
exit condition.
Reviewed-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Clean-up clk_set function to prepare the next changes (DDR and clk-stop)
Reviewed-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Remove conditional write of cfg register. Warn if set_clk fails for some
reason. Consistently use host->dev instead of mixing with mmc_dev(mmc)
Reviewed-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

cfg init function overwrite values set in the clk init function
Remove the cfg pokes from the clk init. Actually, trying to use
the CLK_AUTO, like initially tried in clk_init, would break
the card initialization
Reviewed-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

On boot, the clock divider value is 0 which is a weird unsupported value.
For example, accessing the cfg register with this value set would crash
the SoC.

Previous change removed 0 as possible value for CCF but forgot to properly
initialize the register before registering the clock. This leads to the
CCF finding an illegal value, which it complains about.

Initialize the register properly in a standalone patch so the fix can be
picked up if necessary. The change this fixed is: "mmc: meson-gx: remove
CLK_DIVIDER_ALLOW_ZERO clock flag".
Reported-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

amba_id are not supposed to change at runtime. All functions
working with const amba_id. So mark the non-const structs as const.
Signed-off-by: NArvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The intention for this patch is to help folks debug the failure
like this:

dwmmc_rockchip fe320000.dwmmc: IDMAC supports 32-bit address mode.
dwmmc_rockchip fe320000.dwmmc: Using internal DMA controller.
dwmmc_rockchip fe320000.dwmmc: Version ID is 270a
dwmmc_rockchip fe320000.dwmmc: DW MMC controller at irq 28,32 bit
host data width,256 deep fifo
dwmmc_rockchip fe320000.dwmmc: Got CD GPIO
mmc_host mmc0: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual
400000HZ div = 0)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz,
actual 50000000HZ div = 0)
mmc0: new high speed SDHC card at address 0007
mmcblk: probe of mmc0:0007 failed with error -28

The reason may be some buggy userspace daemon miss the disk remove
uevent sometimes so it would finally make the SD card not work.
So from the dmesg it only shows a errno of -28 but still don't understand
what happened.

For quick reproduce this, we could set max_devices to 8 and run

for i in $(seq 1 9); do
  echo "========================" $i
  echo fe320000.dwmmc > /sys/bus/platform/drivers/dwmmc_rockchip/unbind
  sleep .5
  echo fe320000.dwmmc > /sys/bus/platform/drivers/dwmmc_rockchip/bind
  sleep .5
  mount -t vfat /dev/mmcblk0 /mnt
  sleep .5
done

Another possible reason would be the device has more partitions than
what we support, so that they have to increase their max_devices.
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

This will be useful when drivers want to reuse either suspend or
resume callback instead of whole of sdhci_pltfm_pmops.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

This commit provides similar cleanups as commit 83eacdfa ("mmc:
sdhci: disable the clock in sdhci_pltfm_unregister()") did for
unregister hooks.

sdhci-brcmstb.c and sdhci-sirf.c implement their own suspend/resume
hooks to handle pltfm_host->clk.  Move clock handling to sdhci_pltfm.c
so that the drivers can reuse sdhci_pltfm_pmops.

The following drivers did not previously touch pltfm_host->clk during
suspend/resume, but now do:
  - sdhci-bcm-kona.c
  - sdhci-dove.c
  - sdhci-iproc.c
  - sdhci-pxav2.c
  - sdhci-tegra.c
  - sdhci-xenon.c
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Acked-by: NAl Cooper <alcooperx@gmail.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The difference between sdhci_pxav2_remove() and sdhci_pltfm_unregister()
is clk_put().  It will go away by using the managed resource clk, then
sdhci_pltfm_unregister() can be reused.

Also, rename the jump labels to say what the goto does. (Coding style
suggested by Documentation/process/coding-style.rst)
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Currently, the probe function initializes the PHY, but PHY settings
are lost during the sleep state.  Restore the PHY registers when
resuming.

To facilitate this, split sdhci_cdns_phy_init() into the DT parse
part and PHY update part so that the latter can be invoked from the
resume hook.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Support HS400 Enhanced Strobe feature in Xenon.

Enable Enhanced Strobe together with Data Strobe.
Disable Enhanced Strobe when eMMC is not in HS400 mode.
Signed-off-by: NHu Ziji <huziji@marvell.com>
Signed-off-by: NZhoujie Wu <zjwu@marvell.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

TI's implementation of sdhci controller used in DRA7 SoC's has
CRC in responses with length 136 bits. Add quirk to indicate
the controller has CRC in MMC_RSP_136. If this quirk is
set sdhci library shouldn't shift the response present in
SDHCI_RESPONSE register.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Read each register only once and move the code to a separate function so
that it is not jammed against the 80 column margin.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Remove unused clock rate defines. These should not be defined but
requested from the clock framework.

Also correct typo on the DELAY register
Reviewed-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Remove CLK_DIVIDER_ALLOW_ZERO. This flag means that a 1 based divider
with a 0 value will behave as a bypass clock

The mmc divider does not behave like this, a 0 value disables the clock
Remove this flag so CCF never allows a 0 value on this clock

Fixes: 51c5d844 ("MMC: meson: initial support for GX platforms")
Reviewed-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

CCF generic mux will shift the mask using the value defined in shift
Define the mask accordingly
Reviewed-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Instead of passing a block device to
mmc_blk_ioctl[_multi]_cmd(), let's pass struct mmc_blk_data()
so we operate ioctl()s on the MMC block device representation
rather than the vanilla block device.

This saves a little duplicated code and makes it possible to
issue ioctl()s not targeted for a specific block device but
rather for a specific partition/area.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Instead of passing a struct mmc_blk_data * to mmc_blk_part_switch()
let's pass the actual partition type we want to switch to. This
is necessary in order not to have a block device with a backing
mmc_blk_data and request queue and all for every hardware partition,
such as RPMB.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

mmc_blk_ioctl() calls either mmc_blk_ioctl_cmd() or
mmc_blk_ioctl_multi_cmd() and each of these make the same
check. Factor it into a new helper function, call it on
both branches of the switch() statement and save a chunk
of duplicate code.

Cc: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

If we don't have the block layer enabled, we do not present card
status and extcsd in the debugfs.

Debugfs is not ABI, and maintaining files of no relevance for
non-block devices comes at a high maintenance cost if we shall
support it with the block layer compiled out.

The debugfs entries suffer from all the same starvation
issues as the other userspace things, under e.g. a heavy
dd operation.

The expected number of debugfs users utilizing these two
debugfs files is already low as there is an ioctl() to get the
same information using the mmc-tools, and of these few users
the expected number of people using it on SDIO or combo cards
are expected to be zero.

It is therefore logical to move this over to the block layer
when it is enabled, using the new custom requests and issue
it using the block request queue.

On the other hand it moves some debugfs code from debugfs.c
and into block.c.

Tested during heavy dd load by cat:in the status file.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

This function retrieves the status of the card with the default
number of retries. Since the block layer wants to use this, and
since the block layer is a loadable kernel module, we need to
export this symbol.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

We have a data pointer for the ioctl() data, but we need to
pass other data along with the DRV_OP:s, so make this a
void * so it can be reused.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Get rid of boilerplate code by using module_platform_driver macro.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Acked-by: NJan Glauber <jglauber@cavium.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The new lockdep annotations for completions cause a warning in the
mmc test module, in a function that now has four 150 byte structures
on the stack:

drivers/mmc/core/mmc_test.c: In function 'mmc_test_nonblock_transfer.constprop':
drivers/mmc/core/mmc_test.c:892:1: error: the frame size of 1360 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]

The mmc_test_ongoing_transfer function evidently had a similar problem,
and worked around it by using dynamic allocation.

This generalizes the approach used by mmc_test_ongoing_transfer() and
applies it to mmc_test_nonblock_transfer() as well.

Fixes: cd8084f9 ("locking/lockdep: Apply crossrelease to completions")
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Tested-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

eSDHC is not a standard SD host controller. SDHCI_CAPABILITIES_1
register address is 0x44 while it's 0x114 (ESDHC_CAPABILITIES_1)
for eSDHC.
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

SD controller with SDHCI_QUIRK_NO_HISPD_BIT quirk probably
use high speed enable bit for other purpose. So this bit
shouldn't be changed for high speed enabling for this type of
SD controller.
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Now that sdhci_set_bus_width() supports 8-bit bus widths based on the
MMC_CAP_8_BIT_DATA capability flag, replace the sdhci-s3c version with
the generic sdhci version.
Signed-off-by: NMichał Mirosław <mirq-linux@rere.qmqm.pl>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Acked-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Now that sdhci_set_bus_width() supports 8-bit bus widths based on the
MMC_CAP_8_BIT_DATA capability flag, replace the sdhci-pci version with
the generic sdhci version.
Signed-off-by: NMichał Mirosław <mirq-linux@rere.qmqm.pl>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Now that sdhci_set_bus_width() supports 8-bit bus widths based on the
MMC_CAP_8_BIT_DATA capability flag, replace the tegra version with the
generic sdhci version.
Signed-off-by: NMichał Mirosław <mirq-linux@rere.qmqm.pl>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Hosts supporting 8-bit bus are marked accordingly. If MMC_CAP_8_BIT_DATA
is not among host capabilities, 8BITBUS bit will never be set and it
is not cleared in case some non-SDHCI3 host uses it for something else.
Signed-off-by: NMichał Mirosław <mirq-linux@rere.qmqm.pl>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

CQE needs to be off for the host controller to accept non-CQ commands. Turn
off the CQE before sending commands, and ensure it is off in any reset or
power management paths, or re-tuning.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

mmc_return_hold() / mmc_retune_release() are used around a group of
commands to prevent re-tuning between the commands. Re-tuning can still
happen before the first command. In some cases, re-tuning must be
prevented entirely. Add mmc_retune_hold_now() for that purpose. It is
added in preparation for CQE support where it will be used by CQE recovery.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>