1. 02 5月, 2017 1 次提交
  2. 21 3月, 2017 3 次提交
  3. 06 3月, 2017 1 次提交
  4. 28 2月, 2017 1 次提交
  5. 21 2月, 2017 2 次提交
  6. 15 2月, 2017 1 次提交
  7. 08 2月, 2017 1 次提交
  8. 02 2月, 2017 1 次提交
  9. 27 1月, 2017 4 次提交
  10. 02 1月, 2017 1 次提交
  11. 18 12月, 2016 1 次提交
  12. 29 11月, 2016 1 次提交
  13. 09 11月, 2016 1 次提交
  14. 08 11月, 2016 1 次提交
  15. 25 10月, 2016 1 次提交
  16. 17 10月, 2016 2 次提交
  17. 04 10月, 2016 8 次提交
  18. 19 8月, 2016 1 次提交
  19. 17 8月, 2016 1 次提交
  20. 09 8月, 2016 2 次提交
    • M
      drm/edid: Set 8 bpc color depth for displays with "DFP 1.x compliant TMDS". · 210a021d
      Mario Kleiner 提交于
      According to E-EDID spec 1.3, table 3.9, a digital video sink with the
      "DFP 1.x compliant TMDS" bit set is "signal compatible with VESA DFP 1.x
      TMDS CRGB, 1 pixel / clock, up to 8 bits / color MSB aligned".
      
      For such displays, the DFP spec 1.0, section 3.10 "EDID support" says:
      
      "If the DFP monitor only supports EDID 1.X (1.1, 1.2, etc.)
       without extensions, the host will make the following assumptions:
      
       1. 24-bit MSB-aligned RGB TFT
       2. DE polarity is active high
       3. H and V syncs are active high
       4. Established CRT timings will be used
       5. Dithering will not be enabled on the host"
      
      So if we don't know the bit depth of the display from additional
      colorimetry info we should assume 8 bpc / 24 bpp by default.
      
      This patch adds info->bpc = 8 assignement for that case.
      Signed-off-by: NMario Kleiner <mario.kleiner.de@gmail.com>
      Cc: Jani Nikula <jani.nikula@intel.com>
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      210a021d
    • M
      drm/edid: Add 6 bpc quirk for display AEO model 0. · e10aec65
      Mario Kleiner 提交于
      Bugzilla https://bugzilla.kernel.org/show_bug.cgi?id=105331
      reports that the "AEO model 0" display is driven with 8 bpc
      without dithering by default, which looks bad because that
      panel is apparently a 6 bpc DP panel with faulty EDID.
      
      A fix for this was made by commit 013dd9e0
      ("drm/i915/dp: fall back to 18 bpp when sink capability is unknown").
      
      That commit triggers new regressions in precision for DP->DVI and
      DP->VGA displays. A patch is out to revert that commit, but it will
      revert video output for the AEO model 0 panel to 8 bpc without
      dithering.
      
      The EDID 1.3 of that panel, as decoded from the xrandr output
      attached to that bugzilla bug report, is somewhat faulty, and beyond
      other problems also sets the "DFP 1.x compliant TMDS" bit, which
      according to DFP spec means to drive the panel with 8 bpc and
      no dithering in absence of other colorimetry information.
      
      Try to make the original bug reporter happy despite the
      faulty EDID by adding a quirk to mark that panel as 6 bpc,
      so 6 bpc output with dithering creates a nice picture.
      
      Tested by injecting the edid from the fdo bug into a DP connector
      via drm_kms_helper.edid_firmware and verifying the 6 bpc + dithering
      is selected.
      
      This patch should be backported to stable.
      Signed-off-by: NMario Kleiner <mario.kleiner.de@gmail.com>
      Cc: stable@vger.kernel.org
      Cc: Jani Nikula <jani.nikula@intel.com>
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      e10aec65
  21. 23 5月, 2016 4 次提交
  22. 15 4月, 2016 1 次提交