Because, there is no reason for it not to be const.

v1: original
v2: fix compile break in vmwgfx, and couple related cleanups suggested
    by Ville Syrjälä
Signed-off-by: NRob Clark <robdclark@gmail.com>
Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

All the gem based kms drivers really want the same function to
destroy a dumb framebuffer backing storage object.

So give it to them and roll it out in all drivers.

This still leaves the option open for kms drivers which don't use GEM
for backing storage, but it does decently simplify matters for gem
drivers.
Acked-by: NInki Dae <inki.dae@samsung.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Cc: Ben Skeggs <skeggsb@gmail.com>
Reviwed-by: NRob Clark <robdclark@gmail.com>
Cc: Alex Deucher <alexdeucher@gmail.com>
Acked-by: NPatrik Jakobsson <patrik.r.jakobsson@gmail.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: NDave Airlie <airlied@redhat.com>

This patch merges host1x_syncpt_cpu_incr to host1x_syncpt_incr() as
they are in practise doing the same thing. host1x_syncpt_incr() is
also modified to return error codes. User space interface is modified
accordingly to pass return values.
Signed-off-by: NArto Merilainen <amerilainen@nvidia.com>
Acked-By: NTerje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

DRIVER_BUS_PLATFORM is not a DRM driver feature flag, it must not be set
in the driver's driver_features field.
Signed-off-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Add the missing unlock before return from function host1x_drm_init() and
host1x_drm_exit() in the error handling case.
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>

Since the Tegra DRM driver doesn't use the drm_irq_install() helper, the
irq_enabled flag needs to be set manually in order to make functionality
such as the DRM_IOCTL_WAIT_VBLANK work properly.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>

Add client driver for 2D device, and IOCTLs to pass work to host1x
channel for 2D.

Also adds functions that can be called to access sync points from
DRM.
Signed-off-by: NArto Merilainen <amerilainen@nvidia.com>
Signed-off-by: NTerje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: NThierry Reding <thierry.reding@avionic-design.de>
Tested-by: NThierry Reding <thierry.reding@avionic-design.de>
Tested-by: NErik Faye-Lund <kusmabite@gmail.com>
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>

This patch introduces a memory manager for tegra drm and moves
existing parts to use it. As cma framebuffer helpers can no more
be used, this patch adds also a separate framebuffer driver for
tegra.
Signed-off-by: NArto Merilainen <amerilainen@nvidia.com>
Signed-off-by: NTerje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: NThierry Reding <thierry.reding@avionic-design.de>
Tested-by: NThierry Reding <thierry.reding@avionic-design.de>
Tested-by: NErik Faye-Lund <kusmabite@gmail.com>
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>

Remove second host1x driver, and bind tegra-drm to the new host1x
driver. The logic to parse device tree and track clients is moved
to drm.c.
Signed-off-by: NArto Merilainen <amerilainen@nvidia.com>
Signed-off-by: NTerje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: NThierry Reding <thierry.reding@avionic-design.de>
Tested-by: NThierry Reding <thierry.reding@avionic-design.de>
Tested-by: NErik Faye-Lund <kusmabite@gmail.com>
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>

Both host1x and drm drivers have host1x structures. This patch
renames the host1x structure under drm to follow name host1x_drm.
Signed-off-by: NArto Merilainen <amerilainen@nvidia.com>
Signed-off-by: NTerje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: NThierry Reding <thierry.reding@avionic-design.de>
Tested-by: NThierry Reding <thierry.reding@avionic-design.de>
Tested-by: NErik Faye-Lund <kusmabite@gmail.com>
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>

Make drm part of host1x driver.
Signed-off-by: NArto Merilainen <amerilainen@nvidia.com>
Signed-off-by: NTerje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: NThierry Reding <thierry.reding@avionic-design.de>
Tested-by: NThierry Reding <thierry.reding@avionic-design.de>
Tested-by: NErik Faye-Lund <kusmabite@gmail.com>
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>

This list is most useful to inspect whether framebuffer reference
counting works as expected. The code is loosely based on the i915
implementation.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>

All the necessary support bits like .mode_set_base() and VBLANK are now
available, so page-flipping case easily be implemented on top.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>

Implement support for the VBLANK IOCTL. Note that Tegra is somewhat
special in this case because it doesn't use the generic IRQ support
provided by the DRM core (DRIVER_HAVE_IRQ) but rather registers one
interrupt handler for each display controller.

While at it, clean up the way that interrupts are enabled to ensure
that the VBLANK interrupt only gets enabled when required.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>

Migrate Tegra clock support to drivers/clk/tegra, this involves
moving:
1. definition of tegra_cpu_car_ops to clk.c
2. definition of reset functions to clk-peripheral.c
3. change parent of cpu clock.
4. Remove legacy clock initialization.
5. Initialize clocks using DT.
6. Remove all instance of mach/clk.h
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
[swarren: use to_clk_periph_gate().]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This commit adds a KMS driver for the Tegra20 SoC. This includes basic
support for host1x and the two display controllers found on the Tegra20
SoC. Each display controller can drive a separate RGB/LVDS output.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Tested-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NMark Zhang <markz@nvidia.com>
Reviewed-by: NMark Zhang <markz@nvidia.com>
Tested-by: NMark Zhang <markz@nvidia.com>
Tested-and-acked-by: NAlexandre Courbot <acourbot@nvidia.com>
Acked-by: NTerje Bergstrom <tbergstrom@nvidia.com>
Tested-by: NTerje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>