- 31 7月, 2014 6 次提交
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由 Benjamin Gaignard 提交于
Generic Display Pipeline are one of the compositor input sub-devices. GDP are dedicated to graphic input like RGB plans. GDP is part of Compositor hardware block which will be introduce later. A sti_layer structure is used to abstract GDP calls from Compositor. Signed-off-by: NBenjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: NRob Clark <robdclark@gmail.com>
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由 Benjamin Gaignard 提交于
TVout hardware block is responsible to dispatch the data flow coming from compositor block to any of the output (HDMI or Analog TV). It control when output are start/stop and configure according the require flow path. TVout is the parent of HDMI and HDA drivers and bind them at runtime. Tvout is mapped on drm_encoder structure. One encoder is created for each of the sub-devices and link to their connector/bridge Signed-off-by: NBenjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: NRob Clark <robdclark@gmail.com>
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由 Benjamin Gaignard 提交于
Add driver to support analog TV ouput. HDA driver is mapped on drm_bridge and drm_connector structures. Signed-off-by: NBenjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: NRob Clark <robdclark@gmail.com>
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由 Benjamin Gaignard 提交于
Add driver for HDMI output. HDMI PHY registers are mixed into HDMI device registers and their is only one IRQ for all this hardware block. That is why PHYs aren't using phy framework but only a thin hdmi_phy_ops structure with start and stop functions. HDMI driver is mapped on drm_bridge and drm_connector structures. Signed-off-by: NBenjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: NRob Clark <robdclark@gmail.com>
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由 Benjamin Gaignard 提交于
Video Traffic Advance Communication Rx and Tx drivers are designed for inter-die communication. Signed-off-by: NBenjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: NRob Clark <robdclark@gmail.com>
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由 Benjamin Gaignard 提交于
Video Time Generator drivers are used to synchronize the compositor and tvout hardware IPs by providing line count, sample count, synchronization signals (HSYNC, VSYNC) and top and bottom fields indication. VTG are used by pair for each data path (main or auxiliary) one for master and one for slave. Signed-off-by: NBenjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: NRob Clark <robdclark@gmail.com>
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