The IMX/MXC selects USE_OF at architecture level, so the OF dependency
at individual SoC pinctrl driver level can just be dropped.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

As we now grab IRQs also without first reserving the GPIO
line, let's print the mapped IRQ unconditionally in the
debugfs file as well.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Rename the sync_1 group to sync as the device has a single sync pin
group for the DU, move the cde_disp mux array right after the
corresponding pins array, and split the clk_in pins in three separate
groups as the pins can be used independently.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

On OMAPs the IO ring must be rearmed each time the pad wakeup
configuration is changed. So call pcs_soc->rearm() from
pcs_irq_set().

As pinctrl-single is now an interrupt controller in some cases,
we should follow the standards and keep the interrupts enabled
constantly, and not just for wake-up events. The tracking of
runtime vs wake-up interrupts can be handled separately for
the automated runtime PM solution when we have it in the
future.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
[tony@atomide.com: removed wrong comment, updated description]
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add code to support the specific pin arrangements of the Freescale IMX50 SoC.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The #define for the maximum number of GPIO blocks was retrieved
into pinctrl-at91.c by implicit inclusion of <mach/gpio.h>
from <linux/gpio.h> creating a dependency on machine-local
<mach/gpio.h>. Break the depenency by copying this single
define into the driver.
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This removes a test whether the 'desc' variable is NULL.
This possibility has already been eliminated by the
below test earlier in the loop:

                if (desc == NULL) {
                        dev_warn(pctldev->dev,
                                 "could not get pin desc for pin %d\n",
                                 pins[i]);
                        continue;
                }

Found with Coverity: CID #1090078
Signed-off-by: NMichael Opdenacker <michael.opdenacker@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The commit: "pinctrl: imx: Use struct type for pins" relaced
pin->input_reg by pin->input_val wrongly, fix it at this commit.
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

In case of error, the function devm_ioremap_nocache() returns NULL
pointer not ERR_PTR(). The IS_ERR() test in the return value check
should be replaced with NULL test.
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

imx27 pincontrol driver using the imx1 core driver. The DT bindings are
similar to other imx pincontrol drivers.
Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Core driver for register formats of imx1/imx21/imx27 processors.

The pins of those processors are grouped into ports. Each port has 32
pins. The pins mux configuration is controlled by registers with 1 or 2
bit per pin, depending on the specific control register.
Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add PFC support for the r8a7791 SoC V2 including pin groups for
on-chip devices such as MSIOF, SCIF, USB, MMC, SDHI, DU.
Signed-off-by: NHisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: NKunihito Higashiyama <kunihito.higashiyama.ur@renesas.com>
Signed-off-by: NYoshikazu Fujikawa <yoshikazu.fujikawa.ue@renesas.com>
Signed-off-by: NNobuyuki HIRAI <nobuyuki.hirai.xe@renesas.com>
Signed-off-by: NShinobu Uehara <shinobu.uehara.xc@renesas.com>
Signed-off-by: NKoji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: NRyo Kataoka <ryo.kataoka.wt@renesas.com>
[damm@opensource.se: Forward ported to upstream, minor fixes]
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Add CAN data and clock pin groups to R8A7778 PFC driver.
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The data structure of_match_ptr() protects is always compiled in.
Hence of_match_ptr() is not needed.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

module_platform_driver() makes the code simpler by eliminating
boilerplate code.
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch fix the error handling in tb10x_pinctrl_probe():
 - devm_ioremap_resource() return ERR_PTR() and never return NULL
 - remove the dev_err call to avoid redundant error message
 - pinctrl_register() returns NULL not ERR_PTR()
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Looks like we need a little bit of arch specific handling
with the generic IRQ. Fix the issue with an ifdef the
same way as other drivers do.

ARM needs things set to IRQF_VALID, which also then sets
noprobe. Others seem to use just irq_set_noprobe().

Otherwise we can get:

drivers/pinctrl/pinctrl-single.c: In function 'pcs_irqdomain_map':
drivers/pinctrl/pinctrl-single.c:1750:2: error: implicit declaration of function 'set_irq_flags' [-Werror=implicit-function-declaration]
drivers/pinctrl/pinctrl-single.c:1750:21: error: 'IRQF_VALID' undeclared (first use in this function)
drivers/pinctrl/pinctrl-single.c:1750:34: error: 'IRQF_PROBE' undeclared (first use in this function)
Reported-by: NRandy Dunlap <rdunlap@infradead.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The gpio interrupt controller on Rockchip socs can do edge triggers only
for single edges but not both. Nevertheless a lot of gpio users rely on
the availability of both-edge triggered interrupts - i.e. gpio-keys.

Therefore implement a solution similar to pinctrl-coh901 re-setting the
triggering edge depending on the gpio value in the interrupt demuxer.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Besides the pull registers sitting in a separate place, the rk3188 also
has the peculiarity that the pull registers of the first bank are split
and the first half is sitting in the register space of the pmu.

Therefore this adds a special bank-type for the first bank, to handle
the two register sources.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The check limiting bias options to supported ones is already
done thru rockchip_pinconf_pull_valid. Therefore this check is
redundant and can be removed.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

There are Rockchip SoCs, namely the rk3188, that combine a set of
regular banks with banks that need special handling for some settings.

Therefore add the possibility for the driver to handle more than one
bank type.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Further investigation of the different Rockchip SoCs showed that
the differences especially in the pull settings are quite deep.
As further patches will show, the register layout for the pulls of
the rk3188 is quite strange. Also it is to assume, that later
Rockchip SoCs may introduce even more quirks in this regard, making
it hard to support all of those using the current generic pull_*
variables.

Therefore move the driver to hold the type of controller in an enum
and do the handling according to it in the necessary places. Also
instead of calculating the register in the get and set pull functions
move it to a type-specific callback.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This fixes a typo which left twsi config3 option enabled.

Cc: stable@vger.kernel.org
Signed-off-by: NRoel Kluin <roel.kluin@gmail.com>
Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The pinmux driver of the Abilis Systems TB10x platform based on ARC700 CPUs.
Used to control the pinmux and is a prerequisite for the GPIO driver.
Signed-off-by: NChristian Ruppert <christian.ruppert@abilis.com>
Signed-off-by: NPierrick Hascoet <pierrick.hascoet@abilis.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds the infrastructure required to register non-linear gpio
ranges through gpiolib and the standard GPIO device tree bindings.
Signed-off-by: NChristian Ruppert <christian.ruppert@abilis.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

When an IRQ is started on a GPIO line, mark this GPIO as IRQ in
the gpiolib so we can keep track of the usage centrally.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

When an IRQ is started on a GPIO line, mark this GPIO as IRQ in
the gpiolib so we can keep track of the usage centrally.

Cc: Enric Balletbo i Serra <eballetbo@gmail.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

For omaps, we still have dependencies to the legacy code
for handling the PRM (Power Reset Management) interrupts,
and also for reconfiguring the io wake-up chain after
changes.

Let's pass the PRM interrupt and the rearm functions via
auxdata. Then when at some point we have a proper PRM
driver, we can get the interrupt via device tree and
set up the rearm function as exported function in the
PRM driver.

By using auxdata we can remove a dependency to the
wake-up events for converting omap3 to be device
tree only.

Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Prakash Manjunathappa <prakash.pm@ti.com>
Cc: Roger Quadros <rogerq@ti.com>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: linux-kernel@vger.kernel.org
Reviewed-by: NKevin Hilman <khilman@linaro.org>
Tested-by: NKevin Hilman <khilman@linaro.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The pin control registers can have interrupts for example
for device wake-up. These interrupts can be treated as a
chained interrupt controller as suggested earlier by
Linus Walleij <linus.walleij@linaro.org>.

This patch adds support for interrupts in a way that
should be pretty generic, and works for the omaps that
support wake-up interrupts. On omaps, there's an
interrupt enable and interrupt status bit for each pin.
The two pinctrl domains on omaps share a single interrupt
from the PRM chained interrupt handler. Support for
other similar hardware should be easy to add.

Note that this patch does not attempt to handle the
wake-up interrupts automatically unlike the earlier
patches. This patch allows the device drivers to do
a request_irq() on the wake-up pins as needed. I'll
try to do also a separate generic patch for handling
the wake-up events automatically.

Also note that as this patch makes the pinctrl-single
an irq controller, the current bindings need some
extra trickery to use interrupts from two different
interrupt controllers for the same driver. So it
might be worth waiting a little on the patches
enabling the wake-up interrupts from drivers as there
should be a generic way to handle it coming. And also
there's been discussion of interrupts-extended binding
for using interrupts from multiple interrupt controllers.

In any case, this patch should be ready to go allowing
handling the wake-up interrupts in a generic way, or
separately from the device drivers.

Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Prakash Manjunathappa <prakash.pm@ti.com>
Cc: Roger Quadros <rogerq@ti.com>
Cc: linux-kernel@vger.kernel.org
Cc: Benoît Cousson <bcousson@baylibre.com>
Cc: devicetree@vger.kernel.org
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NHaojian Zhuang <haojian.zhuang@gmail.com>
Reviewed-by: NKevin Hilman <khilman@linaro.org>
Tested-by: NKevin Hilman <khilman@linaro.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The AS3722 is a compact system PMU suitable for mobile phones, tablets etc.

Add a driver to support accessing the GPIO, pinmux and pin configuration
of 8 GPIO pins found on the ams AS3722 through pin control driver and
gpiolib.

The driver will register itself as the pincontrol driver and gpio driver.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Let's replace is_pinconf with flags and add struct pcs_soc_data
so we can support SoC specific features like pin wake-up events.

Done in collaboration with Roger Quadros <rogerq@ti.com>.

Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Prakash Manjunathappa <prakash.pm@ti.com>
Cc: linux-kernel@vger.kernel.org
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NHaojian Zhuang <haojian.zhuang@gmail.com>
Reviewed-by: NKevin Hilman <khilman@linaro.org>
Tested-by: NKevin Hilman <khilman@linaro.org>
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

GPIO output value should be set after the GPIO interrupt is disabled.
Use BIT macro as well.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
[Edited commit message]
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Also avoid use NULL pointer in error message.

v2-changes:
- use port pinter only after checking
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Palmas devices do not support the default bias configuration
and hence removing this option from valid pin config parameters.
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

dn and dp of USB1 can share with UART1(UART1 can route rx,tx to dn and dp pins of USB1).
here we add this pinmux capability.
USB1/UART1 mode selection has dedicated control register in RSC module, here we attach
the register offset of private data of related pin groups.
Signed-off-by: NRong Wang <Rong.Wang@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

USP(Universal Serial Ports) can be UART as commit 5df83111,
this patch defines the USP-based UART function pin groups for prima2.
Signed-off-by: NQipan Li <Qipan.Li@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

the old codes defined uart0_nostreamctrl_pins, but missed pingroup
and padmux definition for it. this patch fixes it.
Signed-off-by: NQipan Li <Qipan.Li@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The data structure of_match_ptr() protects is always compiled in.
Hence of_match_ptr() is not needed.

This is a squash commit of:
pinctrl: at91: Remove redundant of_match_ptr
pinctrl: exynos5440: Remove redundant of_match_ptr
pinctrl: imx35: Remove redundant of_match_ptr
pinctrl: imx51: Remove redundant of_match_ptr
pinctrl: imx53: Remove redundant of_match_ptr
pinctrl: imx6dl: Remove redundant of_match_ptr
pinctrl: imx6q: Remove redundant of_match_ptr
pinctrl: samsung: Remove redundant of_match_ptr
pinctrl: vf610: Remove redundant of_match_ptr
pinctrl: imx6sl: Remove redundant of_match_ptr
pinctrl: plgpio: Remove redundant of_match_ptr
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Recent movement of all configurations of pin in the single call of
pin_config_set(), it is aborting configuration if BIAS_PULL_PIN_DEFAULT
is selected as return of configuration.

The original idea was to just avoid any update on register for pull up/down
configuration if this option is selected.

Fixing this by just bypassing any register update for BIAS_PULL_PIN_DEFAULT
and continuing the remaining configuration.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>