The arndale-octa board was giving "imprecise external aborts" during
boot-up with MCPM enabled. CCI enablement of the boot cluster was found
to be the cause of these aborts (possibly because the secure f/w was not
allowing it). Hence, disable CCI for the arndale-octa board.
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Tested-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: NKevin Hilman <khilman@linaro.org>
Tested-by: NTyler Baker <tyler.baker@linaro.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

We altered the device tree bindings for the Nomadik family of
pin controllers to be standard, this file was merged out-of-order
so we missed fixing this. Fix it up.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

On i.MX28, the MDIO bus is shared between the two FEC instances.
The driver makes sure that the second FEC uses the MDIO bus of the
first FEC. This is done conditionally if FEC_QUIRK_ENET_MAC is set.
However, in newer designs, such as Vybrid or i.MX6SX, each FEC MAC
has its own MDIO bus. Simply removing the quirk FEC_QUIRK_ENET_MAC
is not an option since other logic, triggered by this quirk, is
still needed.

Furthermore, there are board designs which use the same MDIO bus
for both PHY's even though the second bus would be available on the
SoC side. Such layout are popular since it saves pins on SoC side.
Due to the above quirk, those boards currently do work fine. The
boards in the mainline tree with such a layout are:
- Freescale Vybrid Tower with TWR-SER2 (vf610-twr.dts)
- Freescale i.MX6 SoloX SDB Board (imx6sx-sdb.dts)

This patch adds a new quirk FEC_QUIRK_SINGLE_MDIO for i.MX28, which
makes sure that the MDIO bus of the first FEC is used in any case.

However, the boards above do have a SoC with a MDIO bus for each FEC
instance. But the PHY's are not connected in a 1:1 configuration. A
proper device tree description is needed to allow the driver to
figure out where to find its PHY. This patch fixes that shortcoming
by adding a MDIO bus child node to the first FEC instance, along
with the two PHY's on that bus, and making use of the phy-handle
property to add a reference to the PHY's.
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

atmel_lcdfb needs also uses hclk clock, but AT91SAM9263 doesn't have that
specific clock, so use lcd_clk twice. The same was done in
arch/arm/mach-at91/at91sam9263.c
Signed-off-by: NAlexander Stein <alexanders83@web.de>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

The MICBIAS is a supply, should route to MIC while not IN1L.
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

The second property of reg is the length, so correct it for timer.
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

DP PHY now require pmu-system-controller to handle PMU register
to control PHY's power isolation. Adding the same to dp-phy
node.
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>
Reviewed-by: NJingoo Han <jg1.han@samsung.com>
Tested-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

The gpio4 and gpio5 are in 0xf7fc0000 apb which is located in the SM domain.
This patch moves gpio4 and gpio5 to the correct location. This patch also
renames them as the following to match the names we internally used in
marvell:
	gpio4 -> sm_gpio1
	gpio5 -> sm_gpio0
	porte -> portf
	portf -> porte

This also matches what we did for BG2 and BG2CD's SM GPIO.

Cc: stable@vger.kernel.org # 3.16+
Fixes: cedf57fc ("ARM: dts: berlin: add the BG2Q GPIO nodes")
Signed-off-by: NJisheng Zhang <jszhang@marvell.com>
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

There's no card detection for the eMMC, so this patch adds the missing
broken-cd property. This patch also sets bus width as 8 to add
MMC_CAP_8_BIT_DATA in the Host capabilities.

Cc: stable@vger.kernel.org # 3.16+
Fixes: 3047086d ("ARM: dts: berlin: enable SD card reader and eMMC for the BG2Q DMP")
Signed-off-by: NJisheng Zhang <jszhang@marvell.com>
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

On BG2Q, the sdhci2 host uses nfcecc for "io" clk and nfc for "core" clk.
The shdci2 can't work without this patch due to the "core" clk is gated.

Cc: stable@vger.kernel.org # 3.16+
Fixes: 0d859a6a ("ARM: dts: berlin: add the SDHCI nodes for the BG2Q")
Signed-off-by: NJisheng Zhang <jszhang@marvell.com>
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

Revert "ARM: dts: Disable smc91x on n900 until bootloader
dependency is removed". We've now fixed the issues that
caused problems with uninitialized hardware depending on
the bootloader version. Mostly things got fixed with
the following commits:

9a894953 ("ARM: dts: Fix bootloader version dependencies by muxing n900 smc91x pins")
7d2911c4 ("net: smc91x: Fix gpios for device tree based booting")

Note that this only affects the early development boards
with Ethernet that we still have in a few automated boot
test systems. And it's also available supposedly in some
versions of qemu.
Tested-by: NKevin Hilman <khilman@linaro.org>
Tested-by: NAaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: NTony Lindgren <tony@atomide.com>

GPIO2_5 is the reset GPIO for the USB3317 ULPI PHY. Instead of modelling it as
a regulator, the correct approach is to use the 'reset_gpios' property of the
"usb-nop-xceiv" node.

GPIO1_7 is the reset GPIO for the USB2517 USB hub. As we currently don't have
dt bindings to describe a HUB reset, let's keep using the regulator approach.

Rename the regulator to 'reg_hub_reset' to better describe its function and bind
it with the USB host1 port instead.

USB host support has been introduced by commit 9bf206a9 ("ARM: dts:
imx51-babbage: Add USB Host1 support"), which landed in 3.16 and it seems that
USB has only been functional due to previous bootloader initialization.

With this patch applied we can get USB host to work without relying on the
bootloader.

Cc: <stable@vger.kernel.org> # 3.16+
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

64KiB is allocated for qspi dtb partition which is not
sufficient, so updating the partition table size to 512KiB
for device tree partition.

This also aligns the QSPI partition definitions between
kernel and U-Boot.

Fixes: dc2dd5b8 ("ARM: dts: dra7: Add qspi device")
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

From Documentation/devicetree/bindings/clock/imx25-clock.txt:

	cspi1_ipg		78
	cspi2_ipg		79
	cspi3_ipg		80

, so fix the SPI1 clocks accordingly to avoid a kernel hang when trying to
access SPI1.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Commit a04a0b6f ("ARM: dts: imx6qdl: Enable CODA960 VPU") lost the
fix for the CODA960 interrupt order during a rebase before being applied.
This patch adds the missing bit and brings the interrupts and
interrupt-names properties back in sync.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

On LS1021A SoC, the scfg device is in BE mode.
Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

It seems that ever since (536f6b91 mmc: dw_mmc: Reset DMA before
enabling IDMAC) landed upstream that SD cards have been very unhappy
on rk3288-evb.  They were a little unhappy before that change, but
after that change they're REALLY unhappy.

It turns out that the above fix happens to fix a corruption when
reading card information during probe time.  Without the fix we didn't
detect that high speed SD cards could actually support high speed.
With the fix we suddenly detect that they're high speed and we try to
use them at 50MHz.  That doesn't work so well on EVB with the default
drive strength (maybe because there are two physical SD card slots
hooked up to the same pin?).

Fix the problem by bumping up the drive strength of the sdmmc lines.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Fixes: 536f6b91 ("mmc: dw_mmc: Reset DMA before enabling IDMAC")
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The commit b4607572 (ARM: mvebu: remove conflicting muxing on
Armada 370 DB) removes the hog pins muxing. As it is explained in the
commit log it solves a warning a boot time, but more important it also
allows using the Giga port 0 of the board.

Unfortunately in the same time the commit 4904a82a (arm: mvebu:
move Armada 370/XP pinctrl node definition armada-370-xp.dtsi) was
merged and it introduced again the hog pins muxing. Because of it, the
Giga port 0 of the board is no more usable.

This commit remove again the conflicting muxing (hopefully for the
last time).
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
[andrew@lunn.ch: Correct commit IDs]
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Fixes: 4904a82a ("arm: mvebu: move Armada 370/XP pinctrl node definition armada-370-xp.dtsi")

Drop the vendor-prefix from the "ti,system-power-controller" device-tree
property name.

It has been agreed to make "system-power-controller" a standard property
and to drop the vendor-prefix that is currently used by several drivers.

Note that drivers that have used "<vendor>,system-power-controller" in a
released kernel will need to support both versions.
Signed-off-by: NJohan Hovold <johan@kernel.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Benot Cousson <bcousson@baylibre.com>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Felipe Balbi <balbi@ti.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Configure the RTC as system-power controller, which allows the system to
be powered off as well as woken up again on subsequent RTC alarms.

Note that the PMIC needs to be put in SLEEP (rather than OFF) mode to
maintain RTC power.  Specifically, this means that the PMIC
ti,pmic-shutdown-controller property must be left unset in order to be
able to wake up on RTC alarms.

Tested on BeagleBone Black (rev A5).
Signed-off-by: NJohan Hovold <johan@kernel.org>
Reviewed-by: NFelipe Balbi <balbi@ti.com>
Tested-by: NFelipe Balbi <balbi@ti.com>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Benot Cousson <bcousson@baylibre.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Keerthy J <j-keerthy@ti.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Enable am33xx specific RTC features (e.g. PMIC control) by adding
"ti,am3352-rtc" to the compatible property of the rtc node.
Signed-off-by: NJohan Hovold <johan@kernel.org>
Reviewed-by: NFelipe Balbi <balbi@ti.com>
Tested-by: NFelipe Balbi <balbi@ti.com>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Benot Cousson <bcousson@baylibre.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Keerthy J <j-keerthy@ti.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

The lcd0 node for am437x-sk-evm.dts contains bad LCD timings, and while
they seem to work with a quick test, doing for example blank/unblank
will give you a black display.

This patch updates the timings to the 'typical' values from the LCD spec
sheet.

Also, the compatible string is completely bogus, as
"osddisplays,osd057T0559-34ts" is _not_ a 480x272 panel. The panel on
the board is a newhaven one. Update the compatible string to reflect
this. Note that this hasn't caused any issues, as the "panel-dpi"
matches the driver.

Cc: <stable@vger.kernel.org> # v3.17+
Tested-by: NFelipe Balbi <balbi@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

As per the latest Data Manual, for newer samples,
the nominal voltage required for VDD_CORE at OPP_NOM can be
upto 1.06V which was 1.03V earlier.

Update the regulator max voltage constraint for SMPS7,
connected to VDD_CORE, to meet this requirement.

Document reference:
DRA74 Data Manual, SPRS857M - Dec 2012, Revised Oct 2014.
DRA72 Data Manual, SPRS906G - Dec 2012, revised Oct 2014.
Signed-off-by: NRavikumar Kattekola <rk@ti.com>
Acked-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The max expected voltage for VDD_GPU, connected to SMPS6, is 1.25V.
Correct regulator max voltage constraint to meet this requirement.

Document reference: DRA74 Data Manual, SPRS857M - Dec 2012,
		    Revised Oct 2014.

Fixes: c56a831c ("ARM: dts: DRA7: Add TPS659038 PMIC nodes")
Signed-off-by: NRavikumar Kattekola <rk@ti.com>
Acked-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Caused by a copy & paste error. Note that even with
this bug AM437x SK display still works because GPIO
mux mode is always enabled. It's still wrong to mux
somebody else's pin.

Luckily ball D25 (offset 0x238 - gpio5_8) on AM437x
isn't used for anything.

While at that, also replace a pullup with a pulldown
as that gpio should be normally low, not high.

Cc: <stable@vger.kernel.org> # v3.17+
Acked-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Commit f4d809ec55b6 ("ARM: dts: Fix gpmc timings for omap 2430sdp")
added GPMC timings for 2430sdp. This however broke the Ethernet
for some versions of u-boot using a different L3 clock frequency:

set_gpmc_timing_reg: GPMC error! CS5: cs_rd_off: 233 ns, 39 ticks > 31
omap-gpmc 6e000000.gpmc: failed to set gpmc timings for: ethernet

This is because the smsc91x timings from 1.1.4 u-boot overflow the
GPMC registers when booted with 1.1.3 version of u-boot.

Let's fix this issue by using the better timings from u-boot 1.1.3
as they also work on 1.1.4 and are faster.

Note that so far the attempts over the years to calculate the GPMC
timings on the SDP boards have failed probably because of the
unknown latencies added by the FPGA on the debug boards.
Reported-by: NNishanth Menon <nm@ti.com>
Acked-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

This will enable use of physical arch timers on rk3288, where each
core comes out of reset with a different virtual offset.  Using
physical timers will help with SMP booting on coreboot and older
u-boot and should also allow suspend-resume and cpu-hotplug to work on
all firmwares.

Firmware which does initialize the cpu registers properly at boot and
cpu-hotplug can remove this property from the device tree.
Signed-off-by: NSonny Rao <sonnyrao@chromium.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

We now have the physical-timers patches lined up as a dependency in this same
branch, so we can revert the temporary disablement.

This reverts commit b77d4394.
Signed-off-by: NOlof Johansson <olof@lixom.net>

Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>

Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>

Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>

Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>

Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>

Add iommus properties to the device tree nodes for the two display
controllers found on Tegra124. This will allow the display controllers
to map physically non-contiguous buffers to I/O virtual contiguous
address spaces so that they can be used for scan-out.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add iommus properties to the device tree nodes for the two display
controllers found on Tegra114. This will allow the display controllers
to map physically non-contiguous buffers to I/O virtual contiguous
address spaces so that they can be used for scan-out.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add iommus properties to the device tree nodes for the two display
controllers found on Tegra30. This will allow the display controllers to
map physically non-contiguous buffers to I/O virtual contiguous address
spaces so that they can be used for scan-out.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add the memory controller and wire up the interrupt that is used to
report errors. Provide a reference to the memory controller clock and
mark the device as being an IOMMU by adding an #iommu-cells property.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add the device tree node for the memory controller found on Tegra114
SoCs. The memory controller integrates an IOMMU (called SMMU) as well as
various knobs to tweak memory accesses by the various clients.

The old IOMMU device tree node is collapsed into the memory controller
node to more accurately describe the hardware. While this change is
incompatible, the IOMMU driver has never had any users so the change is
not going to cause any breakage.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Collapses the old memory-controller and IOMMU device tree nodes into a
single node to more accurately describe the hardware.

While this is an incompatible change there are no users of the IOMMU on
Tegra, even though a driver has existed for some time.
Signed-off-by: NThierry Reding <treding@nvidia.com>

This patch adds the APB_MISC_GP_MIPI_PAD_CTRL_0 as a pin-control bank on
Tegra124 so the new MIPI pad control group can be muxed between CSI and
DSI_B.
Signed-off-by: NSean Paul <seanpaul@chromium.org>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>