parameter val is not enclosed in parenthesis which is buggy when given an
expression instead of a simple value
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Reviewed-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20170309104154.28295-2-jbrunet@baylibre.com

The macro used gxbb_ prefix for clock definitions. In order
to share the macro between gxbb and meson8b, the prefix must
be moved to gxbb.c.
Signed-off-by: NAlexander Müller <serveralex@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1472319654-59048-6-git-send-email-serveralex@gmail.com

Fractional MPLLs are a superset of the existing AmLogic MPLLs. They add
in a couple of new bitfields for further dividing the clock rate to
achieve rates with fractional hertz.
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

MPLLs are adjustable rate clocks derived from PLLs. On both Meson8b and
GXBB they appear to be only derived from fixed_pll.

Add support for these clock types so that they can be added to their
respective drivers.
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

There are a series of peripheral and system gate clocks that fan out
from the clk81 signal. Add a helper macro to statically initialize these
gate clocks.
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

Remove the composite clock registration function and helpers. Replace
unnecessary configuration struct with static initialization of the
desired clock type.

To preserve git bisect this patch also flips the switch and starts using
of_clk_add_hw_provider instead of the deprecated meson_clk_register_clks
method. As a byproduct clk.c can be deleted.
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

Remove the cpu clock registration function and helpers. Replace
unnecessary configuration struct with static initialization of the
desired clock type.

Ninja rename a5_clk to cpu_clk to better align with cpufreq convention.
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

Remove the fixed factor registration function and helpers. Replace
unnecessary configuration struct with static initialization of the
desired clock type.
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

Remove the pll registration function and helpers. Replace unnecessary
configuration struct with static initialization of the desired clock
type.
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

Remove the fixed_rate registration function and helpers from clkc.[ch].
Replace unnecessary configuration struct with static initialization of
the desired clock type.

While we're here, begin the transition to a proper platform_driver and
call of_clk_add_hw_provider with a shiny new struct clk_hw_onecell_data.
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

This patchset adds the infrastructure for registering and managing the
core clocks found on Amlogic MesonX SoCs. In particular:

- PLLs
- CPU clock
- Fixed rate clocks, fixed factor clocks, ...
Signed-off-by: NCarlo Caione <carlo@endlessm.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>