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  1. 14 6月, 2012 1 次提交
  3. 15 5月, 2012 1 次提交
  5. 24 2月, 2012 3 次提交
    • B
      mips/PCI: get rid of device resource fixups · 96a6b9ad
      由 Bjorn Helgaas 提交于 
      Tell the PCI core about host bridge address translation so it can take
care of bus-to-resource conversion for us.

Here's the wrinkle on Cobalt: we can't generate normal I/O port addresses
on PCI because the GT-64111 doesn't do any address translation, so we have
this:

  CPU I/O port addresses		[io 0x0000-0xffffff]
  PCI bus I/O port addresses	[io 0x10000000-0x10ffffff]

Legacy-mode IDE controllers start out with the legacy bus addresses, e.g.,
0x1f0, assigned by pci_setup_device().  These are outside the range of
addresses GT-64111 can generate on PCI, but pcibios_fixup_device_resources()
converted them to CPU addresses anyway by adding io_offset.  Therefore, we
had to pre-adjust them in cobalt_legacy_ide_fixup().

With io_offset = 0xf0000000, we had this:

  res->start = 0x1f0	initialized in pci_setup_device()
  res->start = 0x100001f0	-= io_offset in cobalt_legacy_ide_fixup()
  res->start = 0x1f0	+= io_offset in pcibios_fixup_device_resources()

The difference after this patch is that the generic pci_bus_to_resource()
only adds the offset if the bus address is inside a host bridge window.
Since 0x1f0 is not a valid bus address and is not inside any windows, it is
unaffected, so we now have this:

  region->start = 0x1f0	initialized in pci_setup_device()
  res->start = 0x1f0	no offset by pci_bus_to_resource()

That means we can remove both pcibios_fixup_device_resources() and
cobalt_legacy_ide_fixup().

I would *rather* set the host bridge offset to zero (which corresponds
to what the GT-64111 actually does), and have both CPU and PCI addresses
of [io 0x10000000-0x10ffffff].  However, that would require changes to
generic code that assumes legacy I/O addresses, such as pic1_io_resource
([io 0x0020-0x00021]), and we'd have to keep a Cobalt IDE fixup.

Of course, none of this changes the fact that references to I/O port
0x1f0 actually go to port 0x100001f0, not 0x1f0, on the Cobalt PCI bus.
Fortunately the VT82C586 IDE controller only decodes the low 24 address
bits, so it does work.

CC: Ralf Baechle <ralf@linux-mips.org>
CC: Yoichi Yuasa <yuasa@linux-mips.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      96a6b9ad
    • B
      mips/PCI: removed unused pci_probe configurability · 14be538c
      由 Bjorn Helgaas 提交于 
      We never assign anything other than PCI_ASSIGN_ALL_BUSSES to pci_probe,
so just remove the indirection.  If configurability is required in the
future, please use the pci_flags/PCI_REASSIGN_ALL_BUS functionality
as is done for powerpc.

CC: Ralf Baechle <ralf@linux-mips.org>
CC: linux-mips@linux-mips.org
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      14be538c
    • B
      mips/PCI: replace pci_probe_only with pci_flags · 29090606
      由 Bjorn Helgaas 提交于 
      Some architectures (alpha, mips, powerpc) have an arch-specific
"pci_probe_only" flag.  Others use PCI_PROBE_ONLY in pci_flags for
the same purpose.  This moves mips to the pci_flags approach so
generic code can use the same test across all architectures.

CC: Ralf Baechle <ralf@linux-mips.org>
CC: linux-mips@linux-mips.org
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      29090606
  7. 21 2月, 2012 1 次提交
  9. 11 1月, 2012 1 次提交
  11. 07 1月, 2012 3 次提交
  13. 01 11月, 2011 1 次提交
  15. 31 3月, 2011 1 次提交
  17. 27 2月, 2010 1 次提交
  19. 23 2月, 2010 2 次提交
  21. 18 9月, 2009 1 次提交
  23. 08 1月, 2009 2 次提交
  25. 10 12月, 2008 1 次提交
  27. 15 10月, 2008 1 次提交
  29. 31 7月, 2008 1 次提交
  31. 20 7月, 2008 1 次提交
  33. 16 7月, 2008 1 次提交
  35. 12 3月, 2008 1 次提交
  37. 20 2月, 2008 2 次提交
  39. 15 12月, 2007 1 次提交
  41. 12 9月, 2007 1 次提交
  43. 11 9月, 2007 1 次提交
  45. 27 8月, 2007 3 次提交
    • R
      [MIPS] HOTPLUG: Make register_pci_controller __devinit. · 606bf782
      由 Ralf Baechle 提交于 
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      606bf782
    • R
      [MIPS] PCI: Remove __devinit attribute from pcibios_fixup_bus. · c4aa2563
      由 Ralf Baechle 提交于 
      Since 96bde06a several callers of
pcibios_resource_to_bus are no longer marked __devinit resulting in a
pile of modpost warnings if PCI && !HOTPLUG:

  MODPOST vmlinux.o
WARNING: vmlinux.o(.text+0x15dde8): Section mismatch: reference to .init.text:pcibios_resource_to_bus (between 'pci_map_rom' and 'pci_map_rom_copy')
WARNING: vmlinux.o(.text+0x15e140): Section mismatch: reference to .init.text:pcibios_resource_to_bus (between 'pci_update_resource' and 'pci_claim_resource')
WARNING: vmlinux.o(.text+0x15f0cc): Section mismatch: reference to .init.text:pcibios_resource_to_bus (between 'pci_setup_cardbus' and 'pci_bus_assign_resources')
WARNING: vmlinux.o(.text+0x15f0f0): Section mismatch: reference to .init.text:pcibios_resource_to_bus (between 'pci_setup_cardbus' and 'pci_bus_assign_resources')
WARNING: vmlinux.o(.text+0x15f114): Section mismatch: reference to .init.text:pcibios_resource_to_bus (between 'pci_setup_cardbus' and 'pci_bus_assign_resources')
WARNING: vmlinux.o(.text+0x15f138): Section mismatch: reference to .init.text:pcibios_resource_to_bus (between 'pci_setup_cardbus' and 'pci_bus_assign_resources')
WARNING: vmlinux.o(.text+0x15f438): Section mismatch: reference to .init.text:pcibios_resource_to_bus (between 'pci_bus_assign_resources' and 'pbus_size_mem')
WARNING: vmlinux.o(.text+0x15f4f4): Section mismatch: reference to .init.text:pcibios_resource_to_bus (between 'pci_bus_assign_resources' and 'pbus_size_mem')

Removing __devinit from pcibios_resource_to_bus make the same necessary
for pcibios_fixup_device_resources as well.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      c4aa2563
    • R
      [MIPS] PCI: Remove __devinit attribute from pcibios_fixup_bus. · 4547d224
      由 Ralf Baechle 提交于 
      Since 96bde06a pcibios_fixup_bus's caller
pci_scan_child_bus is no longer marked __devinit resulting in this modpost
warning if PCI && !HOTPLUG:

  MODPOST vmlinux.o
WARNING: vmlinux.o(.text+0x158b9c): Section mismatch: reference to .init.text:pcibios_fixup_bus (between 'pci_scan_child_bus' and 'pci_scan_bus_parented')
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      4547d224
  47. 13 7月, 2007 1 次提交
  49. 27 4月, 2007 1 次提交
    • T
      [MIPS] Register PCI host bridge resource earlier · 639702bd
      由 Thomas Bogendoerfer 提交于 
      PCI based SNI RM machines have their EISA bus behind an Intel PCI/EISA
bridge. So the PCI IO range must start at 0x0000. Changing that will
break the PCI bus, because i8259.c already has registered it's IO
addresses before the PCI bus gets initialized. Below is a patch,
which will register the PCI host bridge resources inside
register_pci_controller(). It also changes i8259.c to use insert_region(),
because request_resource() will fail, if the IO space of the PIT hanging
of the PCI host bridge (maybe passing the resource parent to
init_i8259_irqs() is a cleaner fix for that).
Signed-off-by: NThomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      639702bd
  51. 27 2月, 2007 1 次提交
  53. 19 2月, 2007 1 次提交
    • R
      [MIPS] Iomap implementation. · 140c1729
      由 Ralf Baechle 提交于 
      This implementation has support for the concept of one separate ioport
address space by PCI domain.  A pointer to the virtual address where
the port space of a domain has been mapped has been added to struct
pci_controller and systems should be fixed to fill in this value. For
single domain systems this will be the same value as passed to
set_io_port_base().
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      140c1729
  55. 01 7月, 2006 1 次提交
  57. 28 6月, 2006 1 次提交
  59. 20 6月, 2006 1 次提交
  61. 30 10月, 2005 1 次提交