Skip to content

cloud-kernel
cloud-kernel

openanolis / cloud-kernel
1 年多 前同步成功

通知 163
Star 36
Fork 7
cloud-kernel
cloud-kernel
切换分支/标签
  1. 12 10月, 2019 1 次提交
  3. 30 7月, 2018 1 次提交
  5. 18 7月, 2018 2 次提交
  7. 12 2月, 2018 1 次提交
  9. 26 1月, 2018 1 次提交
  11. 09 1月, 2017 1 次提交
    • P
      spi: dw: Make debugfs use bus num and make irq name unique · e70002c8
      由 Phil Reid 提交于 
      Instead of using device name it was suggested that bus number was more
appropriate to differentiate debugfs names. Also reduce buffer size to
more realistic 32 bytes instead of 128.

When request_irq is called the bus number may not be assigned. Therefore
the irq name was not unique when dynamic bus number was being used.
As per most of the spi drivers use the device name instead. No other
use of dws->name could be found so it was removed.
Signed-off-by: NPhil Reid <preid@electromag.com.au>
Signed-off-by: NMark Brown <broonie@kernel.org>
      e70002c8
  13. 01 1月, 2017 1 次提交
  15. 11 10月, 2016 1 次提交
  17. 13 9月, 2016 1 次提交
  19. 06 9月, 2016 1 次提交
  21. 23 12月, 2015 1 次提交
  23. 28 10月, 2015 1 次提交
  25. 20 10月, 2015 8 次提交
  27. 18 9月, 2015 2 次提交
  29. 22 8月, 2015 1 次提交
    • M
      spi: dw: Allow interface drivers to limit data I/O to word sizes · c4fe57f7
      由 Michael van der Westhuizen 提交于 
      The commit dd114443 ("spi: dw-spi: Convert 16bit accesses to 32bit
accesses") changed all 16bit accesses in the DW_apb_ssi driver to 32bit.
This, unfortunately, breaks data register access on picoXcell, where the
DW IP needs data register accesses to be word accesses (all other
accesses appear to be OK).

This change introduces a new master variable to allow interface drivers
to specify that 16bit data transfer I/O is required.  This change also
introduces the ability to set this variable via device tree bindings in
the MMIO interface driver.  Both the core and the MMIO interface driver
default to the current 32bit behaviour.

Before this change, on a picoXcell pc3x3:
 spi_master spi32766: interrupt_transfer: fifo overrun/underrun
 m25p80 spi32766.0: error -5 reading 9f
 m25p80: probe of spi32766.0 failed with error -5

After this change:
 m25p80 spi32766.0: m25p40 (512 Kbytes)

Fixes: dd114443 ("spi: dw-spi: Convert 16bit accesses to 32bit accesses")
Signed-off-by: NMichael van der Westhuizen <michael@smart-africa.com>
Reviewed-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>
      c4fe57f7
  31. 26 3月, 2015 1 次提交
  33. 17 3月, 2015 1 次提交
    • T
      spi: dw-spi: Convert 16bit accesses to 32bit accesses · dd114443
      由 Thor Thayer 提交于 
      Altera's Arria10 SoC interconnect requires a 32-bit write for APB
peripherals. The current spi-dw driver uses 16-bit accesses in
some locations. This patch converts all the 16-bit reads and
writes to 32-bit reads and writes.

Additional Documentation to Support this Change:
The DW_apb_ssi databook states:
"All registers in the DW_apb_ssi are addressed at 32-bit boundaries
to remain consistent with the AHB bus. Where the physical size of
any register is less than 32-bits wide, the upper unused bits of
the 32-bit boundary are reserved. Writing to these bits has no
effect; reading from these bits returns 0." [1]

[1] Section 6.1 of dw_apb_ssi.pdf (version 3.22a)

Request for test with platforms using the DesignWare SPI IP.

Tested On:
Altera CycloneV development kit
Altera Arria10 development kit
Compile tested for build errors on x86_64 (allyesconfigs)
Signed-off-by: NThor Thayer <tthayer@opensource.altera.com>
Reviewed-and-tested-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>
      dd114443
  35. 10 3月, 2015 5 次提交
  37. 07 3月, 2015 3 次提交
  39. 26 2月, 2015 1 次提交
    • A
      spi: dw: revisit FIFO size detection again · 9d239d35
      由 Andy Shevchenko 提交于 
      The commit d297933c (spi: dw: Fix detecting FIFO depth) tries to fix the
logic of the FIFO detection based on the description on the comments. However,
there is a slight difference between numbers in TX Level and TX FIFO size.

So, by specification the FIFO size would be in a range 2-256 bytes. From TX
Level prospective it means we can set threshold in the range 0-(FIFO size - 1)
bytes. Hence there are currently two issues:
  a) FIFO size 2 bytes is actually skipped since TX Level is 1 bit and could be
     either 0 or 1 byte;
  b) FIFO size is incorrectly decreased by 1 which already done by meaning of
     TX Level register.

This patch fixes it eventually right.

Fixes: d297933c (spi: dw: Fix detecting FIFO depth)
Reviewed-by: NAxel Lin <axel.lin@ingics.com>
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
      9d239d35
  41. 24 2月, 2015 4 次提交
  43. 08 1月, 2015 1 次提交