- 17 6月, 2017 1 次提交
-
-
由 Thomas Petazzoni 提交于
The XORv2 engines in the AP side of the Armada 7K/8K SoCs are using the AP MS core clock as input, so this commit adds the appropriate clocks properties. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
-
- 19 5月, 2017 2 次提交
-
-
由 Arnd Bergmann 提交于
The way we handle include paths for DT has changed a bit, which broke a file that had an unconventional way to reference a common header file: arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts:47:10: fatal error: include/dt-bindings/input/linux-event-codes.h: No such file or directory This removes the leading "include/" from the path name, which fixes it. Fixes: d5d332d3 ("devicetree: Move include prefixes from arch to separate directory") Signed-off-by: NArnd Bergmann <arnd@arndb.de>
-
由 Olof Johansson 提交于
We use a directory under arch/$ARCH/boot/dts as an include path that has links outside of the subtree to find dt-bindings from under include/dt-bindings. That's been working well, but new DT architectures haven't been adding them by default. Recently there's been a desire to share some of the DT material between arm and arm64, which originally caused developers to create symlinks or relative includes between the subtrees. This isn't ideal -- it breaks if the DT files aren't stored in the exact same hierarchy as the kernel tree, and generally it's just icky. As a somewhat cleaner solution we decided to add a $ARCH/ prefix link once, and allow DTS files to reference dtsi (and dts) files in other architectures that way. Original approach was to create these links under each architecture, but it lead to the problem of recursive symlinks. As a remedy, move the include link directories out of the architecture trees into a common location. At the same time, they can now share one directory and one dt-bindings/ link as well. Fixes: 4027494a ('ARM: dts: add arm/arm64 include symlinks') Reported-by: NRussell King <linux@armlinux.org.uk> Reported-by: NOmar Sandoval <osandov@osandov.com> Reviewed-by: NHeiko Stuebner <heiko@sntech.de> Reviewed-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Tested-by: NHeiko Stuebner <heiko@sntech.de> Acked-by: NRob Herring <robh@kernel.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Mikael Starvik <starvik@axis.com> Cc: Jesper Nilsson <jesper.nilsson@axis.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Frank Rowand <frowand.list@gmail.com> Cc: linux-arch <linux-arch@vger.kernel.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
-
- 10 5月, 2017 1 次提交
-
-
由 yong mao 提交于
configure some fixed mmc parameters Signed-off-by: NYong Mao <yong.mao@mediatek.com> Signed-off-by: NChaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: NMatthias Brugger <matthias.bgg@gmail.com>
-
- 28 4月, 2017 3 次提交
-
-
由 Gregory CLEMENT 提交于
Start to populate the device tree of the Armada 37xx with the pincontrol configuration used on the board providing a dts. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
-
由 Gregory CLEMENT 提交于
Add the nodes for the two pin controller present in the Armada 37xx SoCs. Initially the node was named gpio1 using the same name that for the register range in the datasheet. However renaming it pinctr_nb (nb for North Bridge) makes more sens. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
-
由 Orson Zhai 提交于
SC9860G is a 8 cores of A53 SoC with 4G LTE support SoC from Spreadtrum. According to regular hierarchy of sprd dts, whale2.dtsi contains SoC peripherals IP nodes, sc9860.dtsi contains stuff related to ARM core stuff and sp9860g dts is for the board level. Signed-off-by: NOrson Zhai <orson.zhai@spreadtrum.com> Signed-off-by: NChunyan Zhang <chunyan.zhang@spreadtrum.com> Reviewed-by: NMathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
-
- 25 4月, 2017 2 次提交
-
-
由 Konstantin Porotchkin 提交于
Add fixed clock of 400MHz to system controller driver. This clock is used as SD/eMMC clock source. Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Reviewed-by: NOmri Itach <omrii@marvell.com> Reviewed-by: NHanna Hawa <hannah@marvell.com> [fixed up conflicts, added error handling --rmk] Signed-off-by: NRussell King <rmk+kernel@armlinux.org.uk> Acked-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
-
由 Viresh Kumar 提交于
Compiling the DT file with W=1, DTC warns like follows: Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a unit name, but no reg property Fix this by replacing '@' with '-' as the OPP nodes will never have a "reg" property. Reported-by: NKrzysztof Kozlowski <krzk@kernel.org> Reported-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Suggested-by: NMark Rutland <mark.rutland@arm.com> Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org> Reviewed-by: NChanwoo Choi <cw00.choi@samsung.com> Reviewed-by: NKrzysztof Kozlowski <krzk@kernel.org> Acked-by: NRob Herring <robh@kernel.org> [k.kozlowski: Split patch per ARM and ARM64] Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
-
- 21 4月, 2017 2 次提交
-
-
由 Viresh Kumar 提交于
Compiling the DT file with W=1, DTC warns like follows: Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a unit name, but no reg property Fix this by replacing '@' with '-' as the OPP nodes will never have a "reg" property. Reported-by: NKrzysztof Kozlowski <krzk@kernel.org> Reported-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Suggested-by: NMark Rutland <mark.rutland@arm.com> Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org> Reviewed-by: NChanwoo Choi <cw00.choi@samsung.com> Reviewed-by: NKrzysztof Kozlowski <krzk@kernel.org> Acked-by: NRob Herring <robh@kernel.org> [k.kozlowski: Split patch per ARM and ARM64] Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
-
由 Hoegeun Kwon 提交于
This patch adds the panel device tree node for s6e3hf2 display controller to TM2e dts. Signed-off-by: NHoegeun Kwon <hoegeun.kwon@samsung.com> Reviewed-by: NAndrzej Hajda <a.hajda@samsung.com> Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
-
- 19 4月, 2017 2 次提交
-
-
由 Sudeep Holla 提交于
Commit a8d4636f ("arm64: cacheinfo: Remove CCSIDR-based cache information probing") removed mechanism to extract cache information based on CCSIDR register as the architecture explicitly states no inference about the actual sizes of caches based on CCSIDR registers. Commit 9a802431 ("arm64: cacheinfo: add support to override cache levels via device tree") had already provided options to override cache information from the device tree. This patch adds the information about L1 and L2 caches on all variants of Juno platform. Cc: Will Deacon <will.deacon@arm.com> Cc: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
-
由 Sudeep Holla 提交于
This patch fixes the following set of warnings on juno. smb@08000000 unit name should not have leading 0s sysctl@020000 simple-bus unit address format error, expected "20000" apbregs@010000 simple-bus unit address format error, expected "10000" mmci@050000 simple-bus unit address format error, expected "50000" kmi@060000 simple-bus unit address format error, expected "60000" kmi@070000 simple-bus unit address format error, expected "70000" wdt@0f0000 simple-bus unit address format error, expected "f0000" Acked-by: NLiviu Dudau <liviu.dudau@arm.com> Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
-
- 14 4月, 2017 1 次提交
-
-
由 Rob Herring 提交于
This adds the serial slave device for the WL1835 Bluetooth interface. Signed-off-by: NRob Herring <robh@kernel.org> Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: NMarcel Holtmann <marcel@holtmann.org>
-
- 12 4月, 2017 3 次提交
-
-
由 Antoine Tenart 提交于
Enable the cryptographic engine available in the CP110 master on the Armada 8040 DB. Do not enable the one in the CP110 salve for now, as we do not support multiple cryptographic engines yet. Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
-
由 Antoine Tenart 提交于
Enable the cryptographic engine available in the CP110 master on the Armada 7040 DB. Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
-
由 Antoine Tenart 提交于
Add the description of the crypto engine hardware block for the Marvell Armada 7k and Armada 8k processors; for both the CP110 slave and master. Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
-
- 11 4月, 2017 2 次提交
-
-
由 Gregory CLEMENT 提交于
Also enable it on the Armada 7040 DB and Armada 8040 DB boards. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
-
由 Gregory CLEMENT 提交于
Add the eMMC support for Armada 37xx SoC and enable it in the Armada 3720 DB board. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
-
- 10 4月, 2017 2 次提交
-
-
由 Wang Xiaoyin 提交于
Add pinctrl dtsi file for HiKey960 development board, enable 5 pinmux devices and 1 pinconf device, also include some nodes of configurations for pins. Signed-off-by: NWang Xiaoyin <hw.wangxiaoyin@hisilicon.com> Signed-off-by: NWei Xu <xuwei5@hisilicon.com>
-
由 Wei Xu 提交于
Enable the NIC and SAS nodes for the hip07-d05 board to support related functions. Signed-off-by: NWei Xu <xuwei5@hisilicon.com>
-
- 08 4月, 2017 5 次提交
-
-
由 Wei Xu 提交于
Add 3 SAS host controller nodes and the dependent subctrl node to enable the SAS and SATA function for the hip07 SoC. Signed-off-by: NWei Xu <xuwei5@hisilicon.com>
-
由 Wei Xu 提交于
Add the infiniband node to support the RoCE function on the hip07 SoC. Signed-off-by: NWei Xu <xuwei5@hisilicon.com>
-
由 Wei Xu 提交于
Add MDIO, SerDes, Port and realted HNS nodes to support the network on the hip07 SoC. Signed-off-by: NWei Xu <xuwei5@hisilicon.com>
-
由 Wei Xu 提交于
Add mbigen nodes for the hip07 SoC those will be used for the SAS, XGE and PCIe host controllers. Signed-off-by: NWei Xu <xuwei5@hisilicon.com>
-
由 Andy Yan 提交于
Commit 122682b2abb6 ("arm64: dts: rockchip: Add PX5 Evaluation board") sets the memory size to 2 GB, but this board only has 1 GB DRAM, so change it to the correct value here. Fixes: 122682b2abb6 ("arm64: dts: rockchip: Add PX5 Evaluation board") Signed-off-by: NAndy Yan <andy.yan@rock-chips.com> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
-
- 06 4月, 2017 4 次提交
-
-
由 Icenowy Zheng 提交于
The USB PHY in A64 has a "pmu0" region, which controls the EHCI/OHCI controller pair that can be connected to the PHY0. Add the MMIO region for PHY node. Signed-off-by: NIcenowy Zheng <icenowy@aosc.io> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
-
由 Jiancheng Xue 提交于
Add basic dts files for hi3798cv200-poplar board. Poplar is the first development board compliant with the 96Boards Enterprise Edition TV Platform specification. The board features the Hi3798CV200 with an integrated quad-core 64-bit ARM Cortex A53 processor and high performance Mali T720 GPU. Signed-off-by: NJiancheng Xue <xuejiancheng@hisilicon.com> Reviewed-by: NAlex Elder <elder@linaro.org> Acked-by: NPeter Griffin <peter.griffin@linaro.org> Signed-off-by: NWei Xu <xuwei5@hisilicon.com>
-
由 Daniel Lezcano 提交于
The MMC hosts could be left in an unconsistent or uninitialized state from the firmware. Instead of assuming, the firmware did the right things, let's reset the host controllers. This change fixes a bug when the mmc2/sdio is initialized leading to a hung task: [ 242.704294] INFO: task kworker/7:1:675 blocked for more than 120 seconds. [ 242.711129] Not tainted 4.9.0-rc8-00017-gcf0251f #3 [ 242.716571] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. [ 242.724435] kworker/7:1 D 0 675 2 0x00000000 [ 242.729973] Workqueue: events_freezable mmc_rescan [ 242.734796] Call trace: [ 242.737269] [<ffff00000808611c>] __switch_to+0xa8/0xb4 [ 242.742437] [<ffff000008d07c04>] __schedule+0x1c0/0x67c [ 242.747689] [<ffff000008d08254>] schedule+0x40/0xa0 [ 242.752594] [<ffff000008d0b284>] schedule_timeout+0x1c4/0x35c [ 242.758366] [<ffff000008d08e38>] wait_for_common+0xd0/0x15c [ 242.763964] [<ffff000008d09008>] wait_for_completion+0x28/0x34 [ 242.769825] [<ffff000008a1a9f4>] mmc_wait_for_req_done+0x40/0x124 [ 242.775949] [<ffff000008a1ab98>] mmc_wait_for_req+0xc0/0xf8 [ 242.781549] [<ffff000008a1ac3c>] mmc_wait_for_cmd+0x6c/0x84 [ 242.787149] [<ffff000008a26610>] mmc_io_rw_direct_host+0x9c/0x114 [ 242.793270] [<ffff000008a26aa0>] sdio_reset+0x34/0x7c [ 242.798347] [<ffff000008a1d46c>] mmc_rescan+0x2fc/0x360 [ ... ] Cc: stable@vger.kernel.org Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: NWei Xu <xuwei5@hisilicon.com>
-
由 Geert Uytterhoeven 提交于
The current practice is to not add _clk suffixes to clock node names in DT, as these names are used as the actual clock names. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Acked-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
-
- 05 4月, 2017 5 次提交
-
-
由 Neil Armstrong 提交于
Add HDMI output and connector nodes. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
-
由 Neil Armstrong 提交于
The HDMI modes needs more CMA memory to be reserved at boot-time. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
-
由 Heiner Kallweit 提交于
Now that 3adbf342 "iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs" has added support for the ADC, let's enable it on Odroid C2. Signed-off-by: NHeiner Kallweit <hkallweit1@gmail.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
-
由 Liang Chen 提交于
This patch add rk3328-evb.dts for RK3328 evaluation board. Tested on RK3328 evb. Signed-off-by: NLiang Chen <cl@rock-chips.com> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
-
由 Liang Chen 提交于
This patch adds core dtsi file for Rockchip RK3328 SoCs. Signed-off-by: NLiang Chen <cl@rock-chips.com> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
-
- 04 4月, 2017 4 次提交
-
-
由 Icenowy Zheng 提交于
Allwinner A64 have a dedicated pin controller to manage the PL pin bank. As the driver and the required clock support are added, add the device node for it. Signed-off-by: NIcenowy Zheng <icenowy@aosc.xyz> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
-
由 Icenowy Zheng 提交于
A64 SoC have a CCU (r_ccu) in PRCM block. Add the device node for it. The mux 3 of R_CCU is an internal oscillator, which is 16MHz according to the user manual, and has only 30% accuracy based on our experience on older SoCs. The real mesaured value of it on two Pine64 boards is around 11MHz, which is around 70% of 16MHz. Signed-off-by: NIcenowy Zheng <icenowy@aosc.xyz> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
-
由 Jon Hunter 提交于
Update the Tegra132 flowctrl compatible string to include "nvidia,tegra132-flowctrl" so it is aligned with the flowctrl binding documentation. Signed-off-by: NJon Hunter <jonathanh@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
-
由 Alexandre Courbot 提交于
Add the DT node for the GP10B GPU on Tegra186. Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
-
- 31 3月, 2017 1 次提交
-
-
由 Rob Herring 提交于
dtc recently added PCI bus checks. Fix these warnings. Signed-off-by: NRob Herring <robh@kernel.org> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: NLiviu Dudau <liviu.dudau@arm.com> Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
-