Only process DOEPINT.XferCompl on data packet as DOEPINTn.SetUp can
occur with or without DOEPINT.XferCompl. When DOEPINT.SetUp occurs
with DOEPINT.XferCompl, only DOEPINT.SetUp needs to be handled.

Moreover, ignore DOEPINT.XferCompl when it occurs with
DOEPINT.StupPktRcvd as driver needs to wait for DOEPINT.SetUp to
continue.
Tested-by: NRobert Baldyga <r.baldyga@samsung.com>
Acked-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NMian Yousaf Kaukab <yousaf.kaukab@intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

In preparation of combining the dwc2/s3c-hsotg driver in a single
DRD driver, the defines in dwc2/hw.h needs to get updated so that
the s3c-hsotg driver can use them.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
[ jh,rb - For gadget part only: ]
Tested-by: NJingoo Han <jg1.han@samsung.com>
Tested-by: NRobert Baldyga <r.baldyga@samsung.com>
[ pz - Tested host part only. ]
Signed-off-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

The DWC2 driver should now be in good enough shape to move out of
staging. I have stress tested it overnight on RPI running mass
storage and Ethernet transfers in parallel, and for several days
on our proprietary PCI-based platform.
Signed-off-by: NPaul Zimmerman <paulz@synopsys.com>
Cc: Felipe Balbi <balbi@ti.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

The HWCFG4 register stores the supported utmi width values (8, 16 or
both). This commit reads that value and validates the configured value
against that.

If no (valid) value is given, the parameter defaulted to 8 bits
previously.  However, the documentation for dwc2_core_params_struct
suggests that the default should have been 16. Also, the pci bindings
explicitely set the value to 16, so this commit changes the default to
16 bits (if supported, 8 bits otherwise).

With the default changed, the value set in pci.c is changed to -1 to
make it autodetected as well.
Signed-off-by: NMatthijs Kooijman <matthijs@stdin.nl>
Acked-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Bits 16-31 are reserved, so the old code just reads the whole register to
get bits 0-15, assuming the reserved bits would be 0 (which seems true
on current hardware, but who knows...).

This commit properly masks out the reserved bits when reading and
doesn't touch the reserved bits while writing.
Signed-off-by: NMatthijs Kooijman <matthijs@stdin.nl>
Acked-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Various register fields wider than one bit have constants defined for
their value. Previously, these registers would define the values as they
appear in the register, so shifted to the right to the position the
value appears in the register.

This commit changes those constants to their natural values (e.g, 0, 1,
2, etc.), as they are after shifting the register value to the right.
This also changes all relevant code to shift the values before comparing
them with constants.

This has the advantage that the values can be stored in smaller
variables (now they always require a u32) and makes the handling of
these values more consistent with other register fields that represent
natural numbers instead of enumerations (e.g., number of host channels).
Signed-off-by: NMatthijs Kooijman <matthijs@stdin.nl>
Acked-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

A generic set of FIFOSIZE_* constants is defined which applies to all
fifo size and offset registers. It is already used for both the
GNPTXFSIZ and HPTXFSIZ registers, but it applies to DPTXFSIZN as well.
Some of these also had specific constants defined. This patch removes
the specific constants and documents to use the generic constants.

Note that the removed constants weren't actually used. Instead, most of
the related code uses hardcoded masks and shifts. But given that
subsequent patches will be moving that code around and introducing the
constants in the process, this patch leaves those untouched.

Also note that the GRXFSIZ register also contains a fifo size, but
there is no corresponding start address register (it is always the first
fifo in memory), the layout of the GRXFSIZ register is different and
cannot use the same constants.
Signed-off-by: NMatthijs Kooijman <matthijs@stdin.nl>
Acked-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

The dwc2 driver sets the value of the DWC2 GAHBCFG register to 0x6,
which is GAHBCFG_HBSTLEN_INCR4. But different platforms may require
different values. In particular, the Broadcom 2835 SOC used in the
Raspberry Pi needs a value of 0x10, otherwise the DWC2 controller
stops working after a short period of heavy USB traffic.

So this patch adds another driver parameter named 'ahbcfg'. The
default value is 0x6. Any platform needing a different value should
add a DT attribute to set it.

This patch also removes the 'ahb_single' driver parameter, since
that bit can now be set using 'ahbcfg'.

This patch does not add DT support to platform.c, I will leave that
to whoever owns the first platform that needs a non-default value.
(Stephen?)
Signed-off-by: NPaul Zimmerman <paulz@synopsys.com>
Tested-by: NStephen Warren <swarren@wwwdotorg.org>
Reviewed-by: NMatthijs Kooijman <matthijs@stdin.nl>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

The core code provides basic services for accessing and managing
the DWC_otg hardware. These services are used by both the Host
Controller Driver and (in future) the Peripheral Controller Driver.
Signed-off-by: NPaul Zimmerman <paulz@synopsys.com>
Reviewed-by: NFelipe Balbi <balbi@ti.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>