1. 13 6月, 2018 1 次提交
  2. 01 6月, 2018 12 次提交
    • S
      KVM: PPC: Book3S PR: Enable kvmppc_get/set_one_reg_pr() for HTM registers · deeb879d
      Simon Guo 提交于
      We need to migrate PR KVM during transaction and userspace will use
      kvmppc_get_one_reg_pr()/kvmppc_set_one_reg_pr() APIs to get/set
      transaction checkpoint state. This patch adds support for that.
      
      So far, QEMU on PR KVM doesn't fully function for migration but the
      savevm/loadvm can be done against a RHEL72 guest. During savevm/
      loadvm procedure, the kvm ioctls will be invoked as well.
      
      Test has been performed to savevm/loadvm for a guest running
      a HTM test program:
      https://github.com/justdoitqd/publicFiles/blob/master/test-tm-mig.cSigned-off-by: NSimon Guo <wei.guo.simon@gmail.com>
      Signed-off-by: NPaul Mackerras <paulus@ozlabs.org>
      deeb879d
    • S
      KVM: PPC: Book3S PR: Support TAR handling for PR KVM HTM · 7284ca8a
      Simon Guo 提交于
      Currently guest kernel doesn't handle TAR facility unavailable and it
      always runs with TAR bit on. PR KVM will lazily enable TAR. TAR is not
      a frequent-use register and it is not included in SVCPU struct.
      
      Due to the above, the checkpointed TAR val might be a bogus TAR val.
      To solve this issue, we will make vcpu->arch.fscr tar bit consistent
      with shadow_fscr when TM is enabled.
      
      At the end of emulating treclaim., the correct TAR val need to be loaded
      into the register if FSCR_TAR bit is on.
      
      At the beginning of emulating trechkpt., TAR needs to be flushed so that
      the right tar val can be copied into tar_tm.
      
      Tested with:
      tools/testing/selftests/powerpc/tm/tm-tar
      tools/testing/selftests/powerpc/ptrace/ptrace-tm-tar (remove DSCR/PPR
      related testing).
      Signed-off-by: NSimon Guo <wei.guo.simon@gmail.com>
      Signed-off-by: NPaul Mackerras <paulus@ozlabs.org>
      7284ca8a
    • S
      KVM: PPC: Book3S PR: Add guard code to prevent returning to guest with PR=0 and Transactional state · 68ab07b9
      Simon Guo 提交于
      Currently PR KVM doesn't support transaction memory in guest privileged
      state.
      
      This patch adds a check at setting guest msr, so that we can never return
      to guest with PR=0 and TS=0b10. A tabort will be emulated to indicate
      this and fail transaction immediately.
      
      [paulus@ozlabs.org - don't change the TM_CAUSE_MISC definition, instead
       use TM_CAUSE_KVM_FAC_UNAV.]
      Signed-off-by: NSimon Guo <wei.guo.simon@gmail.com>
      Signed-off-by: NPaul Mackerras <paulus@ozlabs.org>
      68ab07b9
    • S
      KVM: PPC: Book3S PR: Add emulation for trechkpt. · e32c53d1
      Simon Guo 提交于
      This patch adds host emulation when guest PR KVM executes "trechkpt.",
      which is a privileged instruction and will trap into host.
      
      We firstly copy vcpu ongoing content into vcpu tm checkpoint
      content, then perform kvmppc_restore_tm_pr() to do trechkpt.
      with updated vcpu tm checkpoint values.
      Signed-off-by: NSimon Guo <wei.guo.simon@gmail.com>
      Signed-off-by: NPaul Mackerras <paulus@ozlabs.org>
      e32c53d1
    • S
      KVM: PPC: Book3S PR: Restore NV regs after emulating mfspr from TM SPRs · 19c585eb
      Simon Guo 提交于
      Currently kvmppc_handle_fac() will not update NV GPRs and thus it can
      return with GUEST_RESUME.
      
      However PR KVM guest always disables MSR_TM bit in privileged state.
      If PR privileged-state guest is trying to read TM SPRs, it will
      trigger TM facility unavailable exception and fall into
      kvmppc_handle_fac().  Then the emulation will be done by
      kvmppc_core_emulate_mfspr_pr().  The mfspr instruction can include a
      RT with NV reg. So it is necessary to restore NV GPRs at this case, to
      reflect the update to NV RT.
      
      This patch make kvmppc_handle_fac() return GUEST_RESUME_NV for TM
      facility unavailable exceptions in guest privileged state.
      Signed-off-by: NSimon Guo <wei.guo.simon@gmail.com>
      Reviewed-by: NPaul Mackerras <paulus@ozlabs.org>
      Signed-off-by: NPaul Mackerras <paulus@ozlabs.org>
      19c585eb
    • S
      KVM: PPC: Book3S PR: Always fail transactions in guest privileged state · 5706340a
      Simon Guo 提交于
      Currently the kernel doesn't use transaction memory.
      And there is an issue for privileged state in the guest that:
      tbegin/tsuspend/tresume/tabort TM instructions can impact MSR TM bits
      without trapping into the PR host. So following code will lead to a
      false mfmsr result:
      	tbegin	<- MSR bits update to Transaction active.
      	beq 	<- failover handler branch
      	mfmsr	<- still read MSR bits from magic page with
      		transaction inactive.
      
      It is not an issue for non-privileged guest state since its mfmsr is
      not patched with magic page and will always trap into the PR host.
      
      This patch will always fail tbegin attempt for privileged state in the
      guest, so that the above issue is prevented. It is benign since
      currently (guest) kernel doesn't initiate a transaction.
      
      Test case:
      https://github.com/justdoitqd/publicFiles/blob/master/test_tbegin_pr.cSigned-off-by: NSimon Guo <wei.guo.simon@gmail.com>
      Signed-off-by: NPaul Mackerras <paulus@ozlabs.org>
      5706340a
    • S
      KVM: PPC: Book3S PR: Emulate mtspr/mfspr using active TM SPRs · 533082ae
      Simon Guo 提交于
      The mfspr/mtspr on TM SPRs(TEXASR/TFIAR/TFHAR) are non-privileged
      instructions and can be executed by PR KVM guest in problem state
      without trapping into the host. We only emulate mtspr/mfspr
      texasr/tfiar/tfhar in guest PR=0 state.
      
      When we are emulating mtspr tm sprs in guest PR=0 state, the emulation
      result needs to be visible to guest PR=1 state. That is, the actual TM
      SPR val should be loaded into actual registers.
      
      We already flush TM SPRs into vcpu when switching out of CPU, and load
      TM SPRs when switching back.
      
      This patch corrects mfspr()/mtspr() emulation for TM SPRs to make the
      actual source/dest be the actual TM SPRs.
      Signed-off-by: NSimon Guo <wei.guo.simon@gmail.com>
      Signed-off-by: NPaul Mackerras <paulus@ozlabs.org>
      533082ae
    • S
      KVM: PPC: Book3S PR: Add math support for PR KVM HTM · 13989b65
      Simon Guo 提交于
      The math registers will be saved into vcpu->arch.fp/vr and corresponding
      vcpu->arch.fp_tm/vr_tm area.
      
      We flush or giveup the math regs into vcpu->arch.fp/vr before saving
      transaction. After transaction is restored, the math regs will be loaded
      back into regs.
      
      If there is a FP/VEC/VSX unavailable exception during transaction active
      state, the math checkpoint content might be incorrect and we need to do
      treclaim./load the correct checkpoint val/trechkpt. sequence to retry the
      transaction. That will make our solution complicated. To solve this issue,
      we always make the hardware guest MSR math bits (shadow_msr) consistent
      with the MSR val which guest sees (kvmppc_get_msr()) when guest msr is
      with tm enabled. Then all FP/VEC/VSX unavailable exception can be delivered
      to guest and guest handles the exception by itself.
      Signed-off-by: NSimon Guo <wei.guo.simon@gmail.com>
      Signed-off-by: NPaul Mackerras <paulus@ozlabs.org>
      13989b65
    • S
      KVM: PPC: Book3S PR: Add transaction memory save/restore skeleton · 8d2e2fc5
      Simon Guo 提交于
      The transaction memory checkpoint area save/restore behavior is
      triggered when VCPU qemu process is switching out/into CPU, i.e.
      at kvmppc_core_vcpu_put_pr() and kvmppc_core_vcpu_load_pr().
      
      MSR TM active state is determined by TS bits:
          active: 10(transactional) or 01 (suspended)
          inactive: 00 (non-transactional)
      We don't "fake" TM functionality for guest. We "sync" guest virtual
      MSR TM active state(10 or 01) with shadow MSR. That is to say,
      we don't emulate a transactional guest with a TM inactive MSR.
      
      TM SPR support(TFIAR/TFAR/TEXASR) has already been supported by
      commit 9916d57e ("KVM: PPC: Book3S PR: Expose TM registers").
      Math register support (FPR/VMX/VSX) will be done at subsequent
      patch.
      
      Whether TM context need to be saved/restored can be determined
      by kvmppc_get_msr() TM active state:
      	* TM active - save/restore TM context
      	* TM inactive - no need to do so and only save/restore
      TM SPRs.
      Signed-off-by: NSimon Guo <wei.guo.simon@gmail.com>
      Suggested-by: NPaul Mackerras <paulus@ozlabs.org>
      Signed-off-by: NPaul Mackerras <paulus@ozlabs.org>
      8d2e2fc5
    • S
      KVM: PPC: Book3S PR: Add kvmppc_save/restore_tm_sprs() APIs · 66c33e79
      Simon Guo 提交于
      This patch adds 2 new APIs, kvmppc_save_tm_sprs() and
      kvmppc_restore_tm_sprs(), for the purpose of TEXASR/TFIAR/TFHAR
      save/restore.
      Signed-off-by: NSimon Guo <wei.guo.simon@gmail.com>
      Signed-off-by: NPaul Mackerras <paulus@ozlabs.org>
      66c33e79
    • S
      KVM: PPC: Book3S PR: Sync TM bits to shadow msr for problem state guest · 95757bfc
      Simon Guo 提交于
      MSR TS bits can be modified with non-privileged instruction such as
      tbegin./tend.  That means guest can change MSR value "silently" without
      notifying host.
      
      It is necessary to sync the TM bits to host so that host can calculate
      shadow msr correctly.
      
      Note, privileged mode in the guest will always fail transactions so we
      only take care of problem state mode in the guest.
      
      The logic is put into kvmppc_copy_from_svcpu() so that
      kvmppc_handle_exit_pr() can use correct MSR TM bits even when preemption
      occurs.
      Signed-off-by: NSimon Guo <wei.guo.simon@gmail.com>
      Signed-off-by: NPaul Mackerras <paulus@ozlabs.org>
      95757bfc
    • S
      KVM: PPC: Book3S PR: Pass through MSR TM and TS bits to shadow_msr · 901938ad
      Simon Guo 提交于
      PowerPC TM functionality needs MSR TM/TS bits support in hardware level.
      Guest TM functionality can not be emulated with "fake" MSR (msr in magic
      page) TS bits.
      
      This patch syncs TM/TS bits in shadow_msr with the MSR value in magic
      page, so that the MSR TS value which guest sees is consistent with actual
      MSR bits running in guest.
      Signed-off-by: NSimon Guo <wei.guo.simon@gmail.com>
      Signed-off-by: NPaul Mackerras <paulus@ozlabs.org>
      901938ad
  3. 31 5月, 2018 1 次提交
    • P
      KVM: PPC: Book3S PR: Allow KVM_PPC_CONFIGURE_V3_MMU to succeed · 9617a0b3
      Paul Mackerras 提交于
      Currently, PR KVM does not implement the configure_mmu operation, and
      so the KVM_PPC_CONFIGURE_V3_MMU ioctl always fails with an EINVAL
      error.  This causes recent kernels to fail to boot as a PR KVM guest
      on POWER9, since recent kernels booted in HPT mode do the
      H_REGISTER_PROC_TBL hypercall, which causes userspace (QEMU) to do
      KVM_PPC_CONFIGURE_V3_MMU, which fails.
      
      This implements a minimal configure_mmu operation for PR KVM.  It
      succeeds only if the MMU is being configured for HPT mode and no
      process table is being registered.  This is enough to get recent
      kernels to boot as a PR KVM guest.
      Reviewed-by: NGreg Kurz <groug@kaod.org>
      Tested-by: NGreg Kurz <groug@kaod.org>
      Signed-off-by: NPaul Mackerras <paulus@ozlabs.org>
      9617a0b3
  4. 22 5月, 2018 1 次提交
    • S
      KVM: PPC: Add giveup_ext() hook to PPC KVM ops · 2e6baa46
      Simon Guo 提交于
      Currently HV will save math regs(FP/VEC/VSX) when trap into host. But
      PR KVM will only save math regs when qemu task switch out of CPU, or
      when returning from qemu code.
      
      To emulate FP/VEC/VSX mmio load, PR KVM need to make sure that math
      regs were flushed firstly and then be able to update saved VCPU
      FPR/VEC/VSX area reasonably.
      
      This patch adds giveup_ext() field to KVM ops. Only PR KVM has non-NULL
      giveup_ext() ops. kvmppc_complete_mmio_load() can invoke that hook
      (when not NULL) to flush math regs accordingly, before updating saved
      register vals.
      
      Math regs flush is also necessary for STORE, which will be covered
      in later patch within this patch series.
      Signed-off-by: NSimon Guo <wei.guo.simon@gmail.com>
      Signed-off-by: NPaul Mackerras <paulus@ozlabs.org>
      2e6baa46
  5. 18 5月, 2018 3 次提交
  6. 19 3月, 2018 1 次提交
  7. 01 2月, 2018 1 次提交
  8. 10 1月, 2018 1 次提交
    • A
      KVM: PPC: Book3S PR: Fix WIMG handling under pHyp · 6c7d47c3
      Alexey Kardashevskiy 提交于
      Commit 96df2267 ("KVM: PPC: Book3S PR: Preserve storage control bits")
      added code to preserve WIMG bits but it missed 2 special cases:
      - a magic page in kvmppc_mmu_book3s_64_xlate() and
      - guest real mode in kvmppc_handle_pagefault().
      
      For these ptes, WIMG was 0 and pHyp failed on these causing a guest to
      stop in the very beginning at NIP=0x100 (due to bd9166ff "KVM: PPC:
      Book3S PR: Exit KVM on failed mapping").
      
      According to LoPAPR v1.1 14.5.4.1.2 H_ENTER:
      
       The hypervisor checks that the WIMG bits within the PTE are appropriate
       for the physical page number else H_Parameter return. (For System Memory
       pages WIMG=0010, or, 1110 if the SAO option is enabled, and for IO pages
       WIMG=01**.)
      
      This hence initializes WIMG to non-zero value HPTE_R_M (0x10), as expected
      by pHyp.
      
      [paulus@ozlabs.org - fix compile for 32-bit]
      
      Cc: stable@vger.kernel.org # v4.11+
      Fixes: 96df2267 "KVM: PPC: Book3S PR: Preserve storage control bits"
      Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru>
      Tested-by: NRuediger Oertel <ro@suse.de>
      Reviewed-by: NGreg Kurz <groug@kaod.org>
      Tested-by: NGreg Kurz <groug@kaod.org>
      Signed-off-by: NPaul Mackerras <paulus@ozlabs.org>
      6c7d47c3
  9. 01 11月, 2017 1 次提交
    • G
      KVM: PPC: Book3S PR: Only install valid SLBs during KVM_SET_SREGS · f4093ee9
      Greg Kurz 提交于
      Userland passes an array of 64 SLB descriptors to KVM_SET_SREGS,
      some of which are valid (ie, SLB_ESID_V is set) and the rest are
      likely all-zeroes (with QEMU at least).
      
      Each of them is then passed to kvmppc_mmu_book3s_64_slbmte(), which
      assumes to find the SLB index in the 3 lower bits of its rb argument.
      When passed zeroed arguments, it happily overwrites the 0th SLB entry
      with zeroes. This is exactly what happens while doing live migration
      with QEMU when the destination pushes the incoming SLB descriptors to
      KVM PR. When reloading the SLBs at the next synchronization, QEMU first
      clears its SLB array and only restore valid ones, but the 0th one is
      now gone and we cannot access the corresponding memory anymore:
      
      (qemu) x/x $pc
      c0000000000b742c: Cannot access memory
      
      To avoid this, let's filter out non-valid SLB entries. While here, we
      also force a full SLB flush before installing new entries. Since SLB
      is for 64-bit only, we now build this path conditionally to avoid a
      build break on 32-bit, which doesn't define SLB_ESID_V.
      Signed-off-by: NGreg Kurz <groug@kaod.org>
      Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NPaul Mackerras <paulus@ozlabs.org>
      f4093ee9
  10. 27 4月, 2017 1 次提交
  11. 20 4月, 2017 3 次提交
  12. 27 1月, 2017 1 次提交
  13. 25 12月, 2016 1 次提交
  14. 27 9月, 2016 2 次提交
    • T
      KVM: PPC: Book3S PR: Support 64kB page size on POWER8E and POWER8NVL · 2365f6b6
      Thomas Huth 提交于
      On POWER8E and POWER8NVL, KVM-PR does not announce support for
      64kB page sizes and 1TB segments yet. Looks like this has just
      been forgotton so far, since there is no reason why this should
      be different to the normal POWER8 CPUs.
      Signed-off-by: NThomas Huth <thuth@redhat.com>
      Signed-off-by: NPaul Mackerras <paulus@ozlabs.org>
      2365f6b6
    • P
      KVM: PPC: Book3S: Treat VTB as a per-subcore register, not per-thread · 88b02cf9
      Paul Mackerras 提交于
      POWER8 has one virtual timebase (VTB) register per subcore, not one
      per CPU thread.  The HV KVM code currently treats VTB as a per-thread
      register, which can lead to spurious soft lockup messages from guests
      which use the VTB as the time source for the soft lockup detector.
      (CPUs before POWER8 did not have the VTB register.)
      
      For HV KVM, this fixes the problem by making only the primary thread
      in each virtual core save and restore the VTB value.  With this,
      the VTB state becomes part of the kvmppc_vcore structure.  This
      also means that "piggybacking" of multiple virtual cores onto one
      subcore is not possible on POWER8, because then the virtual cores
      would share a single VTB register.
      
      PR KVM emulates a VTB register, which is per-vcpu because PR KVM
      has no notion of CPU threads or SMT.  For PR KVM we move the VTB
      state into the kvmppc_vcpu_book3s struct.
      
      Cc: stable@vger.kernel.org # v3.14+
      Reported-by: NThomas Huth <thuth@redhat.com>
      Tested-by: NThomas Huth <thuth@redhat.com>
      Signed-off-by: NPaul Mackerras <paulus@ozlabs.org>
      88b02cf9
  15. 21 7月, 2016 1 次提交
  16. 01 7月, 2016 1 次提交
  17. 20 6月, 2016 1 次提交
  18. 11 5月, 2016 1 次提交
  19. 01 5月, 2016 1 次提交
    • A
      powerpc/mm/hash: Add support for Power9 Hash · 50de596d
      Aneesh Kumar K.V 提交于
      PowerISA 3.0 adds a parition table indexed by LPID. Parition table
      allows us to specify the MMU model that will be used for guest and host
      translation.
      
      This patch adds support with SLB based hash model (UPRT = 0). What is
      required with this model is to support the new hash page table entry
      format and also setup partition table such that we use hash table for
      address translation.
      
      We don't have segment table support yet.
      
      In order to make sure we don't load KVM module on Power9 (since we don't
      have kvm support yet) this patch also disables KVM on Power9.
      Signed-off-by: NAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      50de596d
  20. 02 12月, 2015 1 次提交
  21. 01 12月, 2015 1 次提交
  22. 26 11月, 2015 1 次提交
  23. 28 5月, 2015 1 次提交
  24. 26 5月, 2015 1 次提交