1. 02 3月, 2010 2 次提交
  2. 01 3月, 2010 3 次提交
  3. 28 2月, 2010 1 次提交
  4. 27 2月, 2010 1 次提交
  5. 26 2月, 2010 15 次提交
    • P
      perf_events, x86: Split PMU definitions into separate files · f22f54f4
      Peter Zijlstra 提交于
      Split amd,p6,intel into separate files so that we can easily deal with
      CONFIG_CPU_SUP_* things, needed to make things build now that perf_event.c
      relies on symbols from amd.c
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      LKML-Reference: <new-submission>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      f22f54f4
    • R
      oprofile/x86: fix msr access to reserved counters · cfc9c0b4
      Robert Richter 提交于
      During switching virtual counters there is access to perfctr msrs. If
      the counter is not available this fails due to an invalid
      address. This patch fixes this.
      
      Cc: stable@kernel.org
      Signed-off-by: NRobert Richter <robert.richter@amd.com>
      cfc9c0b4
    • R
      oprofile/x86: use kzalloc() instead of kmalloc() · c17c8fbf
      Robert Richter 提交于
      Cc: stable@kernel.org
      Signed-off-by: NRobert Richter <robert.richter@amd.com>
      c17c8fbf
    • R
      oprofile/x86: fix perfctr nmi reservation for mulitplexing · 68dc819c
      Robert Richter 提交于
      Multiple virtual counters share one physical counter. The reservation
      of virtual counters fails due to duplicate allocation of the same
      counter. The counters are already reserved. Thus, virtual counter
      reservation may removed at all. This also makes the code easier.
      
      Cc: stable@kernel.org
      Signed-off-by: NRobert Richter <robert.richter@amd.com>
      68dc819c
    • N
      oprofile/x86: add comment to counter-in-use warning · 8588d106
      Naga Chumbalkar 提交于
      Currently, oprofile fails silently on platforms where a non-OS entity
      such as the system firmware "enables" and uses a performance
      counter. There is a warning in the code for this case.
      
      The warning indicates an already running counter. If oprofile doesn't
      collect data, then try using a different performance counter on your
      platform to monitor the desired event. Delete the counter from the
      desired event by editing the
      
       /usr/share/oprofile/<cpu_type>/<cpu>/events
      
      file. If the event cannot be monitored by any other counter, contact
      your hardware or BIOS vendor.
      
      Cc: Shashi Belur <shashi-kiran.belur@hp.com>
      Cc: Tony Jones <tonyj@suse.de>
      Signed-off-by: NNaga Chumbalkar <nagananda.chumbalkar@hp.com>
      Signed-off-by: NRobert Richter <robert.richter@amd.com>
      8588d106
    • R
      oprofile/x86: warn user if a counter is already active · 98a2e73a
      Robert Richter 提交于
      This patch generates a warning if a counter is already active.
      
      Implemented for AMD and P6 models. P4 is not supported.
      
      Cc: Naga Chumbalkar <nagananda.chumbalkar@hp.com>
      Cc: Shashi Belur <shashi-kiran.belur@hp.com>
      Cc: Tony Jones <tonyj@suse.de>
      Signed-off-by: NRobert Richter <robert.richter@amd.com>
      98a2e73a
    • R
      oprofile/x86: implement randomization for IBS periodic op counter · ba52078e
      Robert Richter 提交于
      IBS selects an op (execution operation) for sampling by counting
      either cycles or dispatched ops. Better statistical samples can be
      produced by adding a software generated random offset to the periodic
      op counter value with each sample.
      
      This patch adds software randomization to the IBS periodic op
      counter. The lower 12 bits of the 20 bit counter are
      randomized. IbsOpCurCnt is initialized with a 12 bit random value.
      
      There is a work around if the hw can not write to IbsOpCurCnt. Then
      the lower 8 bits of the 16 bit IbsOpMaxCnt [15:0] value are randomized
      in the range of -128 to +127 by adding/subtracting an offset to the
      maximum count (IbsOpMaxCnt).
      
      The linear feedback shift register (LFSR) algorithm is used for
      pseudo-random number generation to have low impact to the memory
      system.
      Signed-off-by: NRobert Richter <robert.richter@amd.com>
      ba52078e
    • S
      oprofile/x86: implement lsfr pseudo-random number generator for IBS · f125be14
      Suravee Suthikulpanit 提交于
      This patch implements a linear feedback shift register (LFSR) for
      pseudo-random number generation for IBS.
      
      For IBS measurements it would be good to minimize memory traffic in
      the interrupt handler since every access pollutes the data
      caches. Computing a maximal period LFSR just needs shifts and ORs.
      
      The LFSR method is good enough to randomize the ops at low
      overhead. 16 pseudo-random bits are enough for the implementation and
      it doesn't matter that the pattern repeats with a fairly short
      cycle. It only needs to break up (hard) periodic sampling behavior.
      
      The logic was designed by Paul Drongowski.
      Signed-off-by: NSuravee Suthikulpanit <suravee.suthikulpanit@amd.com>
      Signed-off-by: NRobert Richter <robert.richter@amd.com>
      f125be14
    • R
      oprofile/x86: implement IBS cpuid feature detection · 64683da6
      Robert Richter 提交于
      This patch adds IBS feature detection using cpuid flags. An IBS
      capability mask is introduced to test for certain IBS features. The
      bit mask is the same as for IBS cpuid feature flags (Fn8000_001B_EAX),
      but bit 0 is used to indicate the existence of IBS.
      
      The patch also changes the handling of the IbsOpCntCtl bit (periodic
      op counter count control). The oprofilefs file for this feature
      (ibs_op/dispatched_ops) will be only exposed if the feature is
      available, also the default for the bit is set to count clock cycles.
      
      In general, the userland can detect the availability of a feature by
      checking for the corresponding file in oprofilefs. If it exists, the
      feature also exists. This may lead to a dynamic file layout depending
      on the cpu type with that the userland has to deal with. Current
      opcontrol is compatible.
      Signed-off-by: NRobert Richter <robert.richter@amd.com>
      64683da6
    • R
      oprofile/x86: remove node check in AMD IBS initialization · 89baaaa9
      Robert Richter 提交于
      Standard AMD systems have the same number of nodes as there are
      northbridge devices. However, there may kernel configurations
      (especially for 32 bit) or system setups exist, where the node number
      is different or it can not be detected properly. Thus the check is not
      reliable and may fail though IBS setup was fine. For this reason it is
      better to remove the check.
      
      Cc: stable <stable@kernel.org>
      Signed-off-by: NRobert Richter <robert.richter@amd.com>
      89baaaa9
    • R
      oprofile/x86: remove OPROFILE_IBS config option · 013cfc50
      Robert Richter 提交于
      OProfile support for IBS is now for several versions in the
      kernel. The feature is stable now and the code can be activated
      permanently.
      
      As a side effect IBS now works also on nosmp configs.
      Signed-off-by: NRobert Richter <robert.richter@amd.com>
      013cfc50
    • P
      perf_events, x86: Remove superflous MSR writes · 6667661d
      Peter Zijlstra 提交于
      We re-program the event control register every time we reset the count,
      this appears to be superflous, hence remove it.
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Arjan van de Ven <arjan@linux.intel.com>
      LKML-Reference: <new-submission>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      6667661d
    • P
      perf_events: Simplify code by removing cpu argument to hw_perf_group_sched_in() · 6e37738a
      Peter Zijlstra 提交于
      Since the cpu argument to hw_perf_group_sched_in() is always
      smp_processor_id(), simplify the code a little by removing this argument
      and using the current cpu where needed.
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: David Miller <davem@davemloft.net>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Frederic Weisbecker <fweisbec@gmail.com>
      LKML-Reference: <1265890918.5396.3.camel@laptop>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      6e37738a
    • S
      perf_events, x86: AMD event scheduling · 38331f62
      Stephane Eranian 提交于
      This patch adds correct AMD NorthBridge event scheduling.
      
      NB events are events measuring L3 cache, Hypertransport traffic. They are
      identified by an event code >= 0xe0. They measure events on the
      Northbride which is shared by all cores on a package. NB events are
      counted on a shared set of counters. When a NB event is programmed in a
      counter, the data actually comes from a shared counter. Thus, access to
      those counters needs to be synchronized.
      
      We implement the synchronization such that no two cores can be measuring
      NB events using the same counters. Thus, we maintain a per-NB allocation
      table. The available slot is propagated using the event_constraint
      structure.
      Signed-off-by: NStephane Eranian <eranian@google.com>
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      LKML-Reference: <4b703957.0702d00a.6bf2.7b7d@mx.google.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      38331f62
    • S
      perf_events: Add new start/stop PMU callbacks · d76a0812
      Stephane Eranian 提交于
      In certain situations, the kernel may need to stop and start the same
      event rapidly. The current PMU callbacks do not distinguish between stop
      and release (i.e., stop + free the resource). Thus, a counter may be
      released, then it will be immediately re-acquired. Event scheduling will
      again take place with no guarantee to assign the same counter. On some
      processors, this may event yield to failure to assign the event back due
      to competion between cores.
      
      This patch is adding a new pair of callback to stop and restart a counter
      without actually release the underlying counter resource. On stop, the
      counter is stopped, its values saved and that's it. On start, the value
      is reloaded and counter is restarted (on x86, actual restart is delayed
      until perf_enable()).
      Signed-off-by: NStephane Eranian <eranian@google.com>
      [ added fallback to ->enable/->disable for all other PMUs
        fixed x86_pmu_start() to call x86_pmu.enable()
        merged __x86_pmu_disable into x86_pmu_stop() ]
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      LKML-Reference: <4b703875.0a04d00a.7896.ffffb824@mx.google.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      d76a0812
  6. 20 2月, 2010 2 次提交
    • F
      hw-breakpoint: Keep track of dr7 local enable bits · 326264a0
      Frederic Weisbecker 提交于
      When the user enables breakpoints through dr7, he can choose
      between "local" or "global" enable bits but given how linux is
      implemented, both have the same effect.
      
      That said we don't keep track how the user enabled the breakpoints
      so when the user requests the dr7 value, we only translate the
      "enabled" status using the global enabled bits. It means that if
      the user enabled a breakpoint using the local enabled bit, reading
      back dr7 will set the global bit and clear the local one.
      
      Apps like Wine expect a full dr7 POKEUSER/PEEKUSER match for emulated
      softwares that implement old reverse engineering protection schemes.
      
      We fix that by keeping track of the whole dr7 value given by the user
      in the thread structure to drop this bug. We'll think about
      something more proper later.
      
      This fixes a 2.6.32 - 2.6.33-x ptrace regression.
      Reported-and-tested-by: NMichael Stefaniuc <mstefani@redhat.com>
      Signed-off-by: NFrederic Weisbecker <fweisbec@gmail.com>
      Acked-by: NK.Prasad <prasad@linux.vnet.ibm.com>
      Cc: Alan Stern <stern@rowland.harvard.edu>
      Cc: Maneesh Soni <maneesh@linux.vnet.ibm.com>
      Cc: Alexandre Julliard <julliard@winehq.org>
      Cc: Rafael J. Wysocki <rjw@sisk.pl>
      Cc: Maciej Rutecki <maciej.rutecki@gmail.com>
      326264a0
    • F
      hw-breakpoints: Accept breakpoints on NULL address · 84d71092
      Frederic Weisbecker 提交于
      Before we had a generic breakpoint API, ptrace was accepting
      breakpoints on NULL address in x86. The new API refuse them,
      without given strong reasons. We need to follow the previous
      behaviour as some userspace apps like Wine need such NULL
      breakpoints to ensure old emulated software protections
      are still working.
      
      This fixes a 2.6.32 - 2.6.33-x ptrace regression.
      Reported-and-tested-by: NMichael Stefaniuc <mstefani@redhat.com>
      Signed-off-by: NFrederic Weisbecker <fweisbec@gmail.com>
      Acked-by: NK.Prasad <prasad@linux.vnet.ibm.com>
      Acked-by: NRoland McGrath <roland@redhat.com>
      Cc: Alan Stern <stern@rowland.harvard.edu>
      Cc: Maneesh Soni <maneesh@linux.vnet.ibm.com>
      Cc: Alexandre Julliard <julliard@winehq.org>
      Cc: Rafael J. Wysocki <rjw@sisk.pl>
      Cc: Maciej Rutecki <maciej.rutecki@gmail.com>
      84d71092
  7. 17 2月, 2010 2 次提交
  8. 16 2月, 2010 1 次提交
  9. 10 2月, 2010 4 次提交
  10. 08 2月, 2010 1 次提交
    • M
      x86/alternatives: Fix build warning · 076dc4a6
      Masami Hiramatsu 提交于
      Fixes these warnings:
      
       arch/x86/kernel/alternative.c: In function 'alternatives_text_reserved':
       arch/x86/kernel/alternative.c:402: warning: comparison of distinct pointer types lacks a cast
       arch/x86/kernel/alternative.c:402: warning: comparison of distinct pointer types lacks a cast
       arch/x86/kernel/alternative.c:405: warning: comparison of distinct pointer types lacks a cast
       arch/x86/kernel/alternative.c:405: warning: comparison of distinct pointer types lacks a cast
      
      Caused by:
      
        2cfa1978: ftrace/alternatives: Introducing *_text_reserved functions
      
      Changes in v2:
        - Use local variables to compare, instead of type casts.
      Reported-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NMasami Hiramatsu <mhiramat@redhat.com>
      Cc: systemtap <systemtap@sources.redhat.com>
      Cc: DLE <dle-develop@lists.sourceforge.net>
      LKML-Reference: <20100205171647.15750.37221.stgit@dhcp-100-2-132.bos.redhat.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      076dc4a6
  11. 04 2月, 2010 6 次提交
    • S
      perf_events, x86: Fix bug in hw_perf_enable() · 447a194b
      Stephane Eranian 提交于
      We cannot assume that because hwc->idx == assign[i], we can avoid
      reprogramming the counter in hw_perf_enable().
      
      The event may have been scheduled out and another event may have been
      programmed into this counter. Thus, we need a more robust way of
      verifying if the counter still contains config/data related to an event.
      
      This patch adds a generation number to each counter on each cpu. Using
      this mechanism we can verify reliabilty whether the content of a counter
      corresponds to an event.
      Signed-off-by: NStephane Eranian <eranian@google.com>
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Mike Galbraith <efault@gmx.de>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      Cc: Frederic Weisbecker <fweisbec@gmail.com>
      LKML-Reference: <4b66dc67.0b38560a.1635.ffffae18@mx.google.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      447a194b
    • P
      bitops: Ensure the compile time HWEIGHT is only used for such · fce877e3
      Peter Zijlstra 提交于
      Avoid accidental misuse by failing to compile things
      Suggested-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      LKML-Reference: <new-submission>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      fce877e3
    • P
      perf_events, x86: Implement intel core solo/duo support · 8c48e444
      Peter Zijlstra 提交于
      Implement Intel Core Solo/Duo, aka.
      Intel Architectural Performance Monitoring Version 1.
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Mike Galbraith <efault@gmx.de>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      Cc: Frederic Weisbecker <fweisbec@gmail.com>
      Cc: Arjan van de Ven <arjan@linux.intel.com>
      LKML-Reference: <new-submission>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      8c48e444
    • M
      kprobes: Check probe address is reserved · 4554dbcb
      Masami Hiramatsu 提交于
      Check whether the address of new probe is already reserved by
      ftrace or alternatives (on x86) when registering new probe.
      If reserved, it returns an error and not register the probe.
      Signed-off-by: NMasami Hiramatsu <mhiramat@redhat.com>
      Cc: systemtap <systemtap@sources.redhat.com>
      Cc: DLE <dle-develop@lists.sourceforge.net>
      Cc: Steven Rostedt <rostedt@goodmis.org>
      Cc: przemyslaw@pawelczyk.it
      Cc: Frederic Weisbecker <fweisbec@gmail.com>
      Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
      Cc: Jim Keniston <jkenisto@us.ibm.com>
      Cc: Mathieu Desnoyers <compudj@krystal.dyndns.org>
      Cc: Jason Baron <jbaron@redhat.com>
      LKML-Reference: <20100202214918.4694.94179.stgit@dhcp-100-2-132.bos.redhat.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      4554dbcb
    • M
      ftrace/alternatives: Introducing *_text_reserved functions · 2cfa1978
      Masami Hiramatsu 提交于
      Introducing *_text_reserved functions for checking the text
      address range is partially reserved or not. This patch provides
      checking routines for x86 smp alternatives and dynamic ftrace.
      Since both functions modify fixed pieces of kernel text, they
      should reserve and protect those from other dynamic text
      modifier, like kprobes.
      
      This will also be extended when introducing other subsystems
      which modify fixed pieces of kernel text. Dynamic text modifiers
      should avoid those.
      Signed-off-by: NMasami Hiramatsu <mhiramat@redhat.com>
      Cc: systemtap <systemtap@sources.redhat.com>
      Cc: DLE <dle-develop@lists.sourceforge.net>
      Cc: Steven Rostedt <rostedt@goodmis.org>
      Cc: przemyslaw@pawelczyk.it
      Cc: Frederic Weisbecker <fweisbec@gmail.com>
      Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
      Cc: Jim Keniston <jkenisto@us.ibm.com>
      Cc: Mathieu Desnoyers <compudj@krystal.dyndns.org>
      Cc: Jason Baron <jbaron@redhat.com>
      LKML-Reference: <20100202214911.4694.16587.stgit@dhcp-100-2-132.bos.redhat.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      2cfa1978
    • M
      kprobes: Disable booster when CONFIG_PREEMPT=y · 615d0ebb
      Masami Hiramatsu 提交于
      Disable kprobe booster when CONFIG_PREEMPT=y at this time,
      because it can't ensure that all kernel threads preempted on
      kprobe's boosted slot run out from the slot even using
      freeze_processes().
      
      The booster on preemptive kernel will be resumed if
      synchronize_tasks() or something like that is introduced.
      Signed-off-by: NMasami Hiramatsu <mhiramat@redhat.com>
      Cc: systemtap <systemtap@sources.redhat.com>
      Cc: DLE <dle-develop@lists.sourceforge.net>
      Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
      Cc: Frederic Weisbecker <fweisbec@gmail.com>
      Cc: Jim Keniston <jkenisto@us.ibm.com>
      Cc: Mathieu Desnoyers <compudj@krystal.dyndns.org>
      Cc: Steven Rostedt <rostedt@goodmis.org>
      LKML-Reference: <20100202214904.4694.24330.stgit@dhcp-100-2-132.bos.redhat.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      615d0ebb
  12. 03 2月, 2010 2 次提交