- 22 7月, 2015 2 次提交
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由 Dan Murphy 提交于
Fix warning: logical ‘or’ of collectively exhaustive tests is always true Change the internal delay check from an 'or' condition to an 'and' condition. Reported-by: NDavid Binderman <dcb314@hotmail.com> Signed-off-by: NDan Murphy <dmurphy@ti.com> Acked-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Stas Sergeev 提交于
fixed_phy_register() currently hardcodes the fixed PHY link to 1, and expects to find a "speed" parameter to provide correct information towards the fixed PHY consumer. In a subsequent change, where we allow "managed" (e.g: (RS)GMII in-band status auto-negotiation) fixed PHYs, none of these parameters can be provided since they will be auto-negotiated, hence, we just provide a zero-initialized fixed_phy_status to fixed_phy_register() which makes it fail when we call fixed_phy_update_regs() since status.speed = 0 which makes us hit the "default" label and error out. Without this change, we would also see potentially inconsistent speed/duplex parameters for fixed PHYs when the link is DOWN. CC: netdev@vger.kernel.org CC: linux-kernel@vger.kernel.org Signed-off-by: NStas Sergeev <stsp@users.sourceforge.net> [florian: add more background to why this is correct and desirable] Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 21 7月, 2015 2 次提交
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由 Shaohui Xie 提交于
We store c45 PHY's id information in c45_ids, so it should be used to check the matching between PHY driver and PHY device for c45 PHY. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Shaohui Xie 提交于
Teranetics TN2020 is compliant with IEEE 802.3an 10 Gigabit. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 18 7月, 2015 1 次提交
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由 Jacob Keller 提交于
Signed-off-by: NJacob Keller <jacob.e.keller@intel.com> Acked-by: NRichard Cochran <richardcochran@gmail.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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- 11 7月, 2015 2 次提交
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由 David Thomson 提交于
Support manually setting the polarity to mdi or mdix Signed-off-by: NDavid Thomson <david.thomson@alliedtelesis.co.nz> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 David Thomson 提交于
Pass the mdix setting from ethtool down to the phy driver, to allow driver specific implementations of manually setting the polarity. Signed-off-by: NDavid Thomson <david.thomson@alliedtelesis.co.nz> Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 09 7月, 2015 1 次提交
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由 Rob Herring 提交于
On UML builds, mdio-mux-mmioreg.c fails to compile: drivers/net/phy/mdio-mux-mmioreg.c:50:3: error: implicit declaration of function ‘ioremap’ [-Werror=implicit-function-declaration] drivers/net/phy/mdio-mux-mmioreg.c:63:3: error: implicit declaration of function ‘iounmap’ [-Werror=implicit-function-declaration] This is due to CONFIG_OF now being user selectable. Add a dependency on HAS_IOMEM to fix this. Signed-off-by: NRob Herring <robh@kernel.org> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: David S. Miller <davem@davemloft.net> Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 29 6月, 2015 4 次提交
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由 Florian Fainelli 提交于
All BCM7xxx integrated Gigabit PHYs have an issue in their MDIO management controller which will make the initial read or write to them to fail and return 0xffff. This is a real issue as the typical first thing we do is read from MII_PHYSID1 and MII_PHYSID2 from get_phy_id() to register a driver for these PHYs. Coupled with the workaround in drivers/net/phy/bcm7xxx.c, this workaround for the MDIO bus controller consists in scanning the list of PHYs to do this initial read workaround for as part of the MDIO bus reset routine which is invoked prior to mdiobus_scan(). Once we have a proper PHY driver/device registered, all workarounds are located there (e.g: power management suspend/resume calls). Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Florian Fainelli 提交于
The initial MDIO read or write towards the BCM7xxx integrated PHY may fail, workaround this by inserting a dummy MII_BMSR read to force the MDIO management controller to see at least one valid transaction and get out of stuck state out of reset. Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Shengzhou Liu 提交于
As some C45 10G PHYs(e.g. Cortina CS4315/CS4340 PHY) have zero Devices In package, current driver can't get correct devices_in_package value by non-zero Devices In package. so let's probe more with zero Devices In package to support more C45 PHYs. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Mugunthan V N 提交于
When limiting phy link speed using "max-speed" to 100mbps or less on a giga bit phy, phy never completes auto negotiation and phy state machine is held in PHY_AN. Fixing this issue by comparing the giga bit advertise though phydev->supported doesn't have it but phy has BMSR_ESTATEN set. So that auto negotiation is restarted as old and new advertise are different and link comes up fine. Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com> Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 25 6月, 2015 1 次提交
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由 Shaohui Xie 提交于
Vitesse VSC8641 is compatible with Vitesse 82xx Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 23 6月, 2015 1 次提交
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由 Shengzhou Liu 提交于
RTL8211F has different register definitions from RTL8211E. Specially it needs to enable TXDLY in case of RGMII. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 11 6月, 2015 2 次提交
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由 Florian Fainelli 提交于
Some Ethernet PHYs/switches such as Broadcom's BCM53125 have a hardware bug which makes them not release the MDIO line during turn-around time. This gets flagged by the UniMAC MDIO controller as a read failure, and we fail the read transaction. Check the MDIO bus phy_ignore_ta_mask bitmask for the PHY we are reading from and if it is listed in this bitmask, ignore the read failure and proceed with returning the data we read out of the controller. Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Gustavo Zacarias 提交于
Add PHY IDs for Davicom DM9161B and DM9161C variants. Tested with a DM9161C on a custom Atmel-based SAM9X25 board in RMII mode. The DM9161B uses the same model id with just the LSB bit of the version id changing (which is masked out). For all intents and purposes they're the same as the DM9161A with an added GPSI mode and better fabrication process. Signed-off-by: NGustavo Zacarias <gustavo@zacarias.com.ar> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 09 6月, 2015 2 次提交
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由 Dan Murphy 提交于
Fix the device tree entries to modify the '_' to '-'. Also changes the names of the internal delay properties from -int- to -internal- as the -int- appeared as a keyword. Signed-off-by: NDan Murphy <dmurphy@ti.com> Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Florian Fainelli 提交于
Update the AFE_TX_CONFIG value to solve marginal rise/fall issues observed when the link is operating in 100BaseT. This workaround applies to GPHY revisions D0, E0 and newer. Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 08 6月, 2015 3 次提交
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由 Jaeden Amero 提交于
Link failures have been observed when using the KSZ9031 with HP 1810-8G and HP 1910-8G network switches. Center the FLP timing at 16ms to help avoid intermittent link failures. >From the KSZ9031RNX and KSZ9031MNX data sheets revision 2.2, section "Auto-Negotiation Timing": The KSZ9031[RNX or MNX] Fast Link Pulse (FLP) burst-to-burst transmit timing for Auto-Negotiation defaults to 8ms. IEEE 802.3 Standard specifies this timing to be 16ms +/-8ms. Some PHY link partners need to receive the FLP with 16ms centered timing; otherwise, there can be intermittent link failures and long link-up times. The PHY data sheet recommends configuring the FLP burst registers after power-up/reset and immediately thereafter restarting auto-negotiation, so we center the FLP timing at 16ms and then restart auto-negotiation in the config_init for KSZ9031. Signed-off-by: NJaeden Amero <jaeden.amero@ni.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Jaeden Amero 提交于
There are some defines for a few pad skew related extended registers. Specify for which MMD Address (dev_addr) they are for. Signed-off-by: NJaeden Amero <jaeden.amero@ni.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Jaeden Amero 提交于
In a few places in this driver, we weren't using const where we could have. Use const more. In addition, change the arrays of strings in ksz9031_config_init() to be not only const, but also static. Signed-off-by: NJaeden Amero <jaeden.amero@ni.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 04 6月, 2015 1 次提交
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由 Dan Murphy 提交于
Add support for the TI dp83867 Gigabit ethernet phy device. The DP83867 is a robust, low power, fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-T, 100BASE-TX and 1000BASE-T Ethernet protocols. Signed-off-by: NDan Murphy <dmurphy@ti.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 01 6月, 2015 1 次提交
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由 Rojhalat Ibrahim 提交于
There have been concerns that the function names gpiod_set_array() and gpiod_get_array() might be confusing to users. One might expect gpiod_get_array() to return array values, while it is actually the array counterpart of gpiod_get(). To be consistent with the single descriptor API we could rename gpiod_set_array() to gpiod_set_array_value(). This makes some function names a bit lengthy: gpiod_set_raw_array_value_cansleep(). Signed-off-by: NRojhalat Ibrahim <imr@rtschenk.de> Acked-by: NAlexandre Courbot <acourbot@nvidia.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 27 5月, 2015 2 次提交
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由 Florian Fainelli 提交于
Update all open-coded tests for all 4 PHY_INTERFACE_MODE_RGMII* values to use the newly introduced helper: phy_interface_is_rgmii. Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Lendacky, Thomas 提交于
When the ethtool command is used to set the speed of the device while the device is down, the check to set the initial mode may fail when the device is brought up, causing failure to bring the device up. Update the code to set the initial mode based on the desired speed if auto-negotiation is disabled. This patch fixes a bug introduced by: d9663c8c ("amd-xgbe-phy: Use phydev advertising field vs supported") Signed-off-by: NTom Lendacky <thomas.lendacky@amd.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 26 5月, 2015 3 次提交
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由 Richard Cochran 提交于
A pair of nested spin locks was introduced in commit 63502b8d "dp83640: Fix receive timestamp race condition". Unfortunately the 'flags' parameter was reused for the inner lock, clobbering the originally saved IRQ state. This patch fixes the issue by changing the inner lock to plain spin_lock without irqsave. Signed-off-by: NRichard Cochran <richardcochran@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Richard Cochran 提交于
Callers of the ext_write function are supposed to hold a mutex that protects the state of the dialed page, but one caller was missing the lock from the very start, and over time the code has been changed without following the rule. This patch cleans up the call sites in violation of the rule. Signed-off-by: NRichard Cochran <richardcochran@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Richard Cochran 提交于
Currently, the calibration function that corrects the initial offsets among multiple devices only works the first time. If the function is called more than once, the calibration fails and bogus offsets will be programmed into the devices. In a well hidden spot, the device documentation tells that trigger indexes 0 and 1 are special in allowing the TRIG_IF_LATE flag to actually work. This patch fixes the issue by using one of the special triggers during the recalibration method. Signed-off-by: NRichard Cochran <richardcochran@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 25 5月, 2015 1 次提交
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由 Florian Fainelli 提交于
While adding support for 7425 PHY in the 7xxx PHY driver, the ID that was used was actually coming from an external PHY: a BCM5461x. Fix this by using the proper ID for the internal 7425 PHY and set the PHY_IS_INTERNAL flag, otherwise consumers of this PHY driver would not be able to properly identify it as such. Fixes: d068b02c ("net: phy: add BCM7425 and BCM7429 PHYs") Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Reviewed-by: NPetri Gynther <pgynther@google.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 21 5月, 2015 1 次提交
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由 Tim Beale 提交于
This is an alternative way of fixing: commit db9683fb ("net: phy: Make sure PHY_RESUMING state change is always processed") When the PHY state transitions from PHY_HALTED to PHY_RESUMING, there are two things we need to do: 1). Re-enable interrupts (and power up the physical link, if powered down) 2). Update the PHY state and net-device based on the link status. There's no strict reason why #1 has to be done from within the main phy_state_machine() function. There is a risk that other changes to the PHY (e.g. setting speed/duplex, which calls phy_start_aneg()) could cause a subsequent state transition before phy_state_machine() has processed the PHY_RESUMING state change. This would leave the PHY with interrupts disabled and/or still in the BMCR_PDOWN/low-power mode. Moving enabling the interrupts and phy_resume() into phy_start() will guarantee this work always gets done. As the PHY is already in the HALTED state and interrupts are disabled, it shouldn't conflict with any work being done in phy_state_machine(). The downside of this change is that if the PHY_RESUMING state is ever entered from anywhere else, it'll also have to repeat this work. Signed-off-by: NTim Beale <tim.beale@alliedtelesis.co.nz> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 17 5月, 2015 2 次提交
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由 Tim Beale 提交于
If phy_start_aneg() was called while the phydev is in the PHY_RESUMING state, then its state would immediately transition to PHY_AN (or PHY_FORCING). This meant the phy_state_machine() never processed the PHY_RESUMING state change, which meant interrupts weren't enabled for the PHY. If the PHY used low-power mode (i.e. using BMCR_PDOWN), then the physical link wouldn't get powered up again. There seems no point for phy_start_aneg() to make the PHY_RESUMING --> PHY_AN transition, as the state machine will do this anyway. I'm not sure about the case where autoneg is disabled, as my patch will change behaviour so that the PHY goes to PHY_NOLINK instead of PHY_FORCING. An alternative solution would be to move the phy_config_interrupt() and phy_resume() work out of the state machine and into phy_start(). The background behind this: we're running linux v3.16.7 and from user-space we want to enable the eth port (i.e. do a SIOCSIFFLAGS ioctl with the IFF_UP flag) and immediately afterward set the interface's speed/duplex. Enabling the interface calls .ndo_open() then phy_start() and the PHY transitions PHY_HALTED --> PHY_RESUMING. Setting the speed/duplex ends up calling phy_ethtool_sset(), which calls phy_start_aneg() (meanwhile the phy_state_machine() hasn't processed the PHY_RESUMING state change yet). Signed-off-by: NTim Beale <tim.beale@alliedtelesis.co.nz> Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Florian Fainelli 提交于
It can be useful to debug the PHY state machine, add dynamic debug prints of the old and new PHY devices state under a friendly format. Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 16 5月, 2015 2 次提交
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由 Florian Fainelli 提交于
RGMII interfaces come in multiple flavors: RGMII with transmit or receive internal delay, no delays at all, or delays in both direction. This change extends the initial check for PHY_INTERFACE_MODE_RGMII to cover all of these variants since EEE should be allowed for any of these modes, since it is a property of the RGMII, hence Gigabit PHY capability more than the RGMII electrical interface and its delays. Fixes: a59a4d19 ("phy: add the EEE support and the way to access to the MMD registers") Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Lendacky, Thomas 提交于
The AMD XGBE device is intended to work with a specific integrated PHY and that PHY is not meant to be a standalone PHY for use by other devices. As such this patch removes the phylib driver and implements the PHY support in the amd-xgbe driver (the majority of the logic from the phylib driver is moved into the amd-xgbe driver). Update the driver version to 1.0.1. Signed-off-by: NTom Lendacky <thomas.lendacky@amd.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 15 5月, 2015 2 次提交
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由 Bert Vermeulen 提交于
This also changes mii_bus.phy_mask to u32 for consistency. Signed-off-by: NBert Vermeulen <bert@biot.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Florian Fainelli 提交于
Update mdiobb_read() to read whether the PHY has a broken turn-around, and if it does, ignore it to make the read succeeed. Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 13 5月, 2015 1 次提交
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由 Niklas Cassel 提交于
Don't do clock-mode-select if clk == NULL, since when building without CONFIG_HAVE_CLK, clk_get returns NULL and clk_get_rate returns 0. Doing clock-mode-select in this cause causes kszphy_probe to return -EINVAL and thus prevents the device from being probed. The original code (before regression) would return 0 when building without CONFIG_HAVE_CLK. Cc: stable <stable@vger.kernel.org> # 3.18+ Fixes: 1fadee0c ("net/phy: micrel: Add clock support for KSZ8021/KSZ8031") Reviewed-by: NFabio Estevam <fabio.estevam@freescale.com> Reviewed-by: NJohan Hovold <johan@kernel.org> Signed-off-by: NNiklas Cassel <niklass@axis.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 11 5月, 2015 1 次提交
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由 Bert Vermeulen 提交于
When the bus id was supplied via a struct platform_device, the driver wasn't handling -1 to mean an unspecified id of the only instance of this driver, as the platform spec requires. Signed-off-by: NBert Vermeulen <bert@biot.com> Reviewed-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 10 5月, 2015 1 次提交
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由 Jean Delvare 提交于
The amd-xgbe driver currently only works with the Seattle SoC, which is ARM64 architecture, so there is no point in building this driver on other architectures except for build testing purpose. The dependency list can be updated later if the driver ever supports other architectures. Signed-off-by: NJean Delvare <jdelvare@suse.de> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 28 4月, 2015 1 次提交
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由 Rojhalat Ibrahim 提交于
Use the new gpiod_get_array and gpiod_put_array functions (added to mainline in the v4.1 merge window) for obtaining and disposing of GPIO descriptors. Cc: David Miller <davem@davemloft.net> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: NRojhalat Ibrahim <imr@rtschenk.de> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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