This is a new phy driver for the SoC USB controllers on the TI DA8xx
family of microcontrollers. The USB 1.1 PHY is just a simple on/off.
The USB 2.0 PHY also allows overriding the VBUS and ID pins.
Signed-off-by: NDavid Lechner <david@lechnology.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add PCI Phy support for Broadcom Northstar2 SoCs.  This driver uses the
interface from the iproc mdio mux driver to enable the devices
respective phys.
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NJon Mason <jonmason@broadcom.com>
Signed-off-by: NPramod Kumar <pramod.kumar@broadcom.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Northstar is a family of SoCs used in home routers. They have USB 2.0
and 3.0 controllers with PHYs that need to be properly initialized.
This driver provides PHY init support in a generic way and can be bound
with an EHCI controller driver.
There are (just a few) registers being defined in bcma header. It's
because DMU/CRU registers will be also needed in other drivers. We will
need them e.g. in PCIe controller/PHY driver and at some point probably
in clock driver for BCM53573 chipset. By using include/linux/bcma/ we
avoid code duplication.
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This patch adds support for Broadcom NS2 SATA3 PHY in existing
Broadcom SATA3 PHY driver.
Signed-off-by: NAnup Patel <anup.patel@broadcom.com>
Acked-by: NFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs.
This hardware block used to be exposed as a pin controller, but it turns
out that this isn't a good fit. The new driver and DT binding much more
accurately describe the hardware and are more flexible in supporting new
SoC generations.
Acked-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Currently, we have a common SATA3 PHY driver for all Broadcom
STB SoCs. This driver can be extended and re-used for Broadcom
iProc SoCs having same SATA3 PHY.

This patch renames existing Broadcom STB SATA3 PHY driver to
common Broadcom SATA3 PHY driver to share this PHY driver across
Broadcom SoCs.
Signed-off-by: NAnup Patel <anup.patel@broadcom.com>
Acked-by: NFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Signed-off-by: NYakir Yang <ykk@rock-chips.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This patch to add a generic PHY driver for ROCKCHIP eMMC PHY.
Access the PHY via registers provided by GRF (general register
files) module.
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Support hi6220 use phy for HiKey board
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This patch adds support for R-Car generation 3 USB2 PHY driver.
This SoC has 3 EHCI/OHCI channels, and the channel 0 is shared
with the HSUSB (USB2.0 peripheral) device. And each channel has
independent registers about the PHYs.

So, the purpose of this driver is:
 1) initializes some registers of SoC specific to use the
    {ehci,ohci}-platform driver.

 2) detects id pin to select host or peripheral on the channel 0.

For now, this driver only supports 1) above.
Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This patch adds the PCIe PHY support for the Broadcom PCIe RC interface
on Cygnus
Signed-off-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NArun Parameswaran <aparames@broadcom.com>
Reviewed-by: NJD (Jiandong) Zheng <jdzheng@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

support usb3.0 phy of mt65xx SoCs
Signed-off-by: NChunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add PHY driver for the internal USB OTG PHY found on NXP
LPC18xx and LPC43xx devices. This driver takes care of
enabling the PHY in CREG (syscon) and setting the required
clock frequency.
Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add a driver for the USB2.0 PHY found on the IMG Pistachio SoC.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: James Hartley <james.hartley@imgtec.com>
Cc: Damien Horsley <Damien.Horsley@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/9728/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add PHY driver for the Marvell HSIC 28nm PHY. This PHY is found in PXA1928
SOC.
Signed-off-by: NRob Herring <robh@kernel.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Add driver for USB 28nm PHY found in Marvell PXA1928 SOC.
Signed-off-by: NRob Herring <robh@kernel.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Supports up to two ports which can each be powered on/off and configured
independently.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

TUSB1210 ULPI PHY has vendor specific register for eye
diagram tuning. On some platforms the system firmware has
set optimized value to it. In order to not loose the
optimized value, the driver stores it during probe and
restores it every time the PHY is powered back on.
Signed-off-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com>
Acked-by: NDavid Cohen <david.a.cohen@linux.intel.com>
Acked-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Unlike previous Allwinner SoCs, there is no central PHY control block
on the A80. Also, OTG support is completely split off into a different
controller.

This adds a new driver to support the regular USB PHYs.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add a minimal driver for dm816x USB. This makes USB work on dm816x
without any other changes needed as it can use the existing musb_dsps
glue layer for the USB controller.

Note that this phy is different from dm814x and am335x.

Cc: Bin Liu <binmlist@gmail.com>
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Felipe Balbi <balbi@ti.com>
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Cc: Paul Bolle <pebolle@tiscali.nl>
Cc: Rusty Russell <rusty@rustcorp.com.au>
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This patch to add a generic PHY driver for ROCKCHIP usb PHYs,
currently this driver can support RK3288. The RK3288 SoC have
three independent USB PHY IPs which are all configured through a
set of registers located in the GRF (general register files)
module.
Signed-off-by: NYunzhi Li <lyz@rock-chips.com>
Tested-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This change adds a support for a 14nm qcom-ufs phy that is
required in platforms that use ufs-qcom controller.
Signed-off-by: NYaniv Gardi <ygardi@codeaurora.org>
Reviewed-by: NDov Levenglick <dovl@codeaurora.org>
Signed-off-by: NChristoph Hellwig <hch@lst.de>

This change adds a support for a 20nm qcom-ufs phy that is required in
platforms that use ufs-qcom controller.
Signed-off-by: NYaniv Gardi <ygardi@codeaurora.org>
Reviewed-by: NDov Levenglick <dovl@codeaurora.org>
Signed-off-by: NChristoph Hellwig <hch@lst.de>

This change adds a generic and common API support for ufs phy QUALCOMM
Technologies. This support provides common code and also points
to specific phy callbacks to differentiate between different behaviors
of frequent use-cases (like power on, power off, phy calibration etc).
Signed-off-by: NYaniv Gardi <ygardi@codeaurora.org>
Reviewed-by: NDov Levenglick <dovl@codeaurora.org>
Signed-off-by: NChristoph Hellwig <hch@lst.de>

The Armada 375 SoC comes with an USB2 host and device controller and
an USB3 controller. The USB cluster control register allows to manage
common features of both USB controllers.

This commit adds a driver integrated in the generic PHY framework to
control this USB cluster feature.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
[ kishon@ti.com : Made it to use the updated devm_phy_create API and
		  soem cosmentic changes in Kconfig file.]
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Acked-by: NJason Cooper <jason@lakedaemon.net>

Add the driver driving the Marvell Berlin USB PHY. This allows to
initialize the PHY and to use it from the USB driver later.
Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe
or USB3 devices.
Signed-off-by: Nalexandre torgue <alexandre.torgue@st.com>
Signed-off-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This driver adds support for USB (1.1 and 2.0) phy for STiH415 and
STiH416 System-On-Chips from STMicroelectronics.
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This is the generic phy driver for the picoPHY ports used by the
USB2 and USB3 Host controllers when controlling usb2/1.1 devices. It
is found on STiH407 SoC family from STMicroelectronics.
Signed-off-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This PHY, though formally being a part of Renesas USBHS controller, contains the
UGCTRL2 register that controls multiplexing of the USB ports (Renesas calls them
channels) to the different USB controllers: channel 0 can be connected to either
PCI EHCI/OHCI or USBHS controllers, channel 2 can be connected to PCI EHCI/OHCI
or xHCI controllers.

This is a new driver for this USB PHY currently already supported under drivers/
usb/phy/. The reason for writing the new driver was the requirement that the
multiplexing  of USB channels to the controller be dynamic, depending on what
USB drivers  are loaded,  rather than static as provided by the old driver. The
infrastructure provided by drivers/phy/phy-core.c  seems to fit that purpose
ideally. The new driver only  supports device tree probing  for now.
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The MiPHY365x is a Generic PHY which can serve various SATA or PCIe
devices. It has 2 ports which it can use for either; both SATA, both
PCIe or one of each in any configuration.
Acked-by: NMark Rutland <mark.rutland@arm.com>
Signed-off-by: NAlexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: NKumar Gala <galak@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The Berlin SoC has a two SATA ports. Add a PHY driver to handle them.

The mode selection can let us think this PHY can be configured to fit
other purposes. But there are reasons to think the SATA mode will be
the only one usable: the PHY registers are only accessible indirectly
through two registers in the SATA range, the PHY seems to be integrated
and no information tells us the contrary. For these reasons, make the
driver a SATA PHY driver.
Signed-off-by: NAntoine Ténart <antoine.tenart@free-electrons.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add a PHY driver for uses with AHCI based SATA controller driver on the
APQ8064 family of SoCs.

This patch is a forward port from Qualcomm's v3.4 andriod kernel.

Tested on IFC6410 board.

CC: Sujit Reddy Thumma <sthumma@codeaurora.org>
Tested-by: NKiran Padwal <kiran.padwal@smartplayin.com>
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add hix5hd2-sata-phy driver on Hisilicon hix5hd2 soc.
Signed-off-by: NJiancheng Xue <xuejiancheng@huawei.com>
Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add support for the Samsung's S5PV210 SoC to the Exynos USB 2.0 PHY driver.
Signed-off-by: NMateusz Krawczuk <m.krawczuk@partner.samsung.com>
[k.debski@samsung.com: cleanup and commit description]
[k.debski@samsung.com: make changes accordingly to the mailing list
comments]
Signed-off-by: NKamil Debski <k.debski@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

ARM based ST Microelectronics's SPEAr1310/40 platforms uses ST's phy (known as
'miphy') for PCIe and SATA. This patch adds drivers for these miphys.

This also adds proper bindings for miphys.
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NPratyush Anand <pratyush.anand@st.com>
Tested-by: NMohit Kumar <mohit.kumar@st.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
[viresh: fixed logs/cclist/checkpatch warnings, broken into smaller patches]
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>

Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs.
The new driver uses the generic PHY framework and will interact
with DWC3 controller present on Exynos5 series of SoCs.

Also, created a new header file in linux/mfd/syscon/ for
Exynos5 SoCs and put the required PMU offset definitions
for the basic available PHYs.
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The top-level phy-samsung-usb2 driver may be configured as a
loadable module, which currently causes link errors because
of the dependency on the exynos{5250,4x12,4210}_usb2_phy_config
symbol. Solving this could be achieved by exporting these
symbols, but as the SoC-specific parts of the driver are not
currently built as modules, it seems better to just link
everything into one module and avoid the need for the export.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NKamil Debski <k.debski@samsung.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

This patch adds support for the APM X-Gene SoC 15Gbps Multi-purpose PHY.
This is the physical layer interface for the corresponding host
controller. Currently, only external clock and Gen3 SATA mode
are supported.
Signed-off-by: NLoc Ho <lho@apm.com>
Signed-off-by: NTuan Phan <tphan@apm.com>
Signed-off-by: NSuman Tripathi <stripathi@apm.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>