- 26 2月, 2010 1 次提交
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由 Luca Barbieri 提交于
The current lock prefix UP/SMP alternative code doesn't allow LOCK_PREFIX to be used in alternatives code. This patch solves the problem by adding a new LOCK_PREFIX_ALTERNATIVE_PATCH macro that only records the lock prefix location but does not emit the prefix. The user of this macro can then start any alternative sequence with "lock" and have it UP/SMP patched. To make this work, the UP/SMP alternative code is changed to do the lock/DS prefix switching only if the byte actually contains a lock or DS prefix. Thus, if an alternative without the "lock" is selected, it will now do nothing instead of clobbering the code. Changes in v2: - Naming change - Change label to not conflict with alternatives Signed-off-by: NLuca Barbieri <luca@luca-barbieri.com> LKML-Reference: <1267005265-27958-2-git-send-email-luca@luca-barbieri.com> Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
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- 17 2月, 2010 1 次提交
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由 Ingo Molnar 提交于
The atomic ops emulation for 32bit legacy CPUs floods the tracer with irq off/on entries. The irq disabled regions are short and therefor not interesting when chasing long irq disabled latencies. Mark them raw and keep them out of the trace. Signed-off-by: NIngo Molnar <mingo@elte.hu> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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- 14 1月, 2010 1 次提交
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由 Brian Gerst 提交于
Using kernel_stack_pointer() allows 32-bit and 64-bit versions to be merged. This is more correct for 64-bit, since the old %rsp is always saved on the stack. Signed-off-by: NBrian Gerst <brgerst@gmail.com> LKML-Reference: <1263397555-27695-1-git-send-email-brgerst@gmail.com> Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
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- 13 1月, 2010 2 次提交
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由 Dave Jones 提交于
Use a macro to define the cache sizes when cachesize > 1 MB. This is less typing, and less prone to introducing bugs like we saw in e02e0e1a, and means we don't have to do maths when adding new non-power-of-2 updates like those seen recently. Signed-off-by: NDave Jones <davej@redhat.com> LKML-Reference: <20100104144735.GA18390@redhat.com> Signed-off-by: NIngo Molnar <mingo@elte.hu>
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由 Linus Torvalds 提交于
This makes gcc use the right register names and instruction operand sizes automatically for the rwsem inline asm statements. So instead of using "(%%eax)" to specify the memory address that is the semaphore, we use "(%1)" or similar. And instead of forcing the operation to always be 32-bit, we use "%z0", taking the size from the actual semaphore data structure itself. This doesn't actually matter on x86-32, but if we want to use the same inline asm for x86-64, we'll need to have the compiler generate the proper 64-bit names for the registers (%rax instead of %eax), and if we want to use a 64-bit counter too (in order to avoid the 15-bit limit on the write counter that limits concurrent users to 32767 threads), we'll need to be able to generate instructions with "q" accesses rather than "l". Since this header currently isn't enabled on x86-64, none of that matters, but we do want to use the xadd version of the semaphores rather than have to take spinlocks to do a rwsem. The mm->mmap_sem can be heavily contended when you have lots of threads all taking page faults, and the fallback rwsem code that uses a spinlock performs abysmally badly in that case. [ hpa: modified the patch to skip size suffixes entirely when they are redundant due to register operands. ] Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org> LKML-Reference: <alpine.LFD.2.00.1001121613560.17145@localhost.localdomain> Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
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- 08 1月, 2010 3 次提交
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由 Brian Gerst 提交于
Merge the now identical code from asm/atomic_32.h and asm/atomic_64.h into asm/atomic.h. Signed-off-by: NBrian Gerst <brgerst@gmail.com> LKML-Reference: <1262883215-4034-4-git-send-email-brgerst@gmail.com> Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
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由 Brian Gerst 提交于
Prepare for merging into asm/atomic.h. Signed-off-by: NBrian Gerst <brgerst@gmail.com> LKML-Reference: <1262883215-4034-3-git-send-email-brgerst@gmail.com> Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
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由 Brian Gerst 提交于
Split atomic64_t functions out into separate headers, since they will not be practical to merge between 32 and 64 bits. Signed-off-by: NBrian Gerst <brgerst@gmail.com> LKML-Reference: <1262883215-4034-2-git-send-email-brgerst@gmail.com> Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
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- 30 12月, 2009 3 次提交
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由 Jan Beulich 提交于
In order to avoid unnecessary chains of branches, rather than implementing memcpy()/memset()'s access to their alternative implementations via a jump, patch the (larger) original function directly. The memcpy() part of this is slightly subtle: while alternative instruction patching does itself use memcpy(), with the replacement block being less than 64-bytes in size the main loop of the original function doesn't get used for copying memcpy_c() over memcpy(), and hence we can safely write over its beginning. Also note that the CFI annotations are fine for both variants of each of the functions. Signed-off-by: NJan Beulich <jbeulich@novell.com> Cc: Nick Piggin <npiggin@suse.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Andrew Morton <akpm@linux-foundation.org> LKML-Reference: <4B2BB8D30200007800026AF2@vpn.id2.novell.com> Signed-off-by: NIngo Molnar <mingo@elte.hu>
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由 Jan Beulich 提交于
In order to avoid unnecessary chains of branches, rather than implementing copy_user_generic() as a function consisting of just a single (possibly patched) branch, instead properly deal with patching call instructions in the alternative instructions framework, and move the patching into the callers. As a follow-on, one could also introduce something like __EXPORT_SYMBOL_ALT() to avoid patching call sites in modules. Signed-off-by: NJan Beulich <jbeulich@novell.com> Cc: Nick Piggin <npiggin@suse.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Andrew Morton <akpm@linux-foundation.org> LKML-Reference: <4B2BB8180200007800026AE7@vpn.id2.novell.com> Signed-off-by: NIngo Molnar <mingo@elte.hu>
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由 Jan Beulich 提交于
The early ioremap fixmap entries cover half (or for 32-bit non-PAE, a quarter) of a page table, yet they got uncondtitionally aligned so far to a 256-entry boundary. This is not necessary if the range of page table entries anyway falls into a single page table. This buys back, for (theoretically) 50% of all configurations (25% of all non-PAE ones), at least some of the lowmem necessarily lost with commit e621bd18. Signed-off-by: NJan Beulich <jbeulich@novell.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Andrew Morton <akpm@linux-foundation.org> LKML-Reference: <4B2BB66F0200007800026AD6@vpn.id2.novell.com> Signed-off-by: NIngo Molnar <mingo@elte.hu>
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- 25 12月, 2009 1 次提交
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由 Russell King 提交于
We can't request the cascade channel before it's been registered, so move it afterwards. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 24 12月, 2009 6 次提交
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由 Russell King 提交于
This fixes a "start_kernel(): bug: interrupts were enabled early". rtc_cmos now takes care of initializing the ISA RTC and reading the current time and date from it; there's no need to repeat that here, thereby causing interrupts to be enabled too early. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
PAGE_KERNEL should not be executable; any area marked executable can be prefetched into the instruction cache. We don't want vmalloc areas to be read in this way. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Markus Pietrek 提交于
With some of the cache rework an address aliasing optimization was added, but this managed to fail on certain mappings resulting in pages with PG_dcache_dirty set never writing back their dcache lines. This patch reverts to the earlier behaviour of simply always writing back when the dirty bit is set. Signed-off-by: NMarkus Pietrek <Markus.Pietrek@emtrion.de> Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Kuninori Morimoto 提交于
o remove unused define o add device name comment Signed-off-by: NKuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Linus Torvalds 提交于
This reverts commit 9f15226e. It's just wrong, and broke resume for Rafael even on a non-AMD CPU. As Rafael says: "... it causes microcode_init_cpu() to be called during resume even for CPUs for which there's no microcode to apply. That, in turn, results in executing request_firmware() (on Intel CPUs at least) which doesn't work at this stage of resume (we have device interrupts disabled, I/O devices are still suspended and so on). If I'm not mistaken, the "if (uci->valid)" logic means "if that CPU is known to us" , so before commit 9f15226e microcode_resume_cpu() was called for all CPUs already in the system during suspend, which was the right thing to do. The commit changed it so that the CPUs without microcode to apply are now treated as "unknown", which is not quite right. The problem this commit attempted to solve has to be handled differently." Bisected-and -requested-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 Russell King 提交于
It is unpredictable to have the same memory mapped using different shared bit settings for ARMv6 and ARMv7 CPUs. Fix this for the CPU write buffer bug test. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 23 12月, 2009 1 次提交
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由 Andrew Morton 提交于
arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c: avoid cross-CPU interrupts by using smp_call_function_any() Presently acpi-cpufreq will perform the MSR read on the first CPU in the mask. That's inefficient if that CPU differs from the current CPU. Because we have to perform a cross-CPU call, but we could have run the rdmsr on the current CPU. So switch to using the new smp_call_function_any(), which will perform the call on the current CPU if that CPU is present in the mask (it is). Cc: "Zhang, Yanmin" <yanmin_zhang@linux.intel.com> Cc: Dave Jones <davej@redhat.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Jaswinder Singh Rajput <jaswinder@kernel.org> Cc: Len Brown <len.brown@intel.com> Cc: Mike Galbraith <efault@gmx.de> Cc: Rusty Russell <rusty@rustcorp.com.au> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Cc: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLen Brown <len.brown@intel.com>
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- 22 12月, 2009 10 次提交
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由 Mike Rapoport 提交于
Commit f74f7e57 (ARM: use flush_kernel_dcache_area() for dmabounce) has broken dmabounce build: CC arch/arm/common/dmabounce.o arch/arm/common/dmabounce.c: In function 'unmap_single': arch/arm/common/dmabounce.c:315: error: implicit declaration of function '__cpuc_flush_kernel_dcache_area' make[2]: *** [arch/arm/common/dmabounce.o] Error 1 Fix it. Signed-off-by: NMike Rapoport <mike@compulab.co.il> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 wanzongshun 提交于
Fix bug of uart0 platfrom data for nuc900 Signed-off-by: Nlijie <eltshanli@gmail.com> Signed-off-by: NWan ZongShun <mcuos.com@gmail.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 wanzongshun 提交于
putc support for nuc900 Signed-off-by: Nlijie <eltshanli@gmail.com> Signed-off-by: NWan ZongShun <mcuos.com@gmail.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 wanzongshun 提交于
fix compiling error for NUC900 Signed-off-by: Nlijie <eltshanli@gmail.com> Signed-off-by: NWan ZongShun <mcuos.com@gmail.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Jean PIHET 提交于
On Oprofile ARMv7 the PMNC_D bit was set to lower the PMU IRQs and so to decrease the risk of errata #628216 from appearing. The effect of setting the PMNC_D bit is that the CCNT counter is divided by 64, making the program counter events count inaccurate. The new OMAP3 r4 cores should have that errata fixed. The PMNC_D bit should not be set, this patch fixes it. Signed-off-by: NJean Pihet <jpihet@mvista.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Alex Chiang 提交于
The x86 and ia64 implementations of the function in $subject are exactly the same. Also, since the arch-specific implementations of setting _PDC have been completely hollowed out, remove the empty shells. Cc: Tony Luck <tony.luck@intel.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Signed-off-by: NAlex Chiang <achiang@hp.com> Signed-off-by: NLen Brown <len.brown@intel.com>
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由 Alex Chiang 提交于
The only thing arch-specific about calling _PDC is what bits get set in the input obj_list buffer. There's no need for several levels of indirection to twiddle those bits. Additionally, since we're just messing around with a buffer, we can simplify the interface; no need to pass around the entire struct acpi_processor * just to get at the buffer. Cc: Tony Luck <tony.luck@intel.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Signed-off-by: NAlex Chiang <achiang@hp.com> Signed-off-by: NLen Brown <len.brown@intel.com>
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由 Alex Chiang 提交于
Both x86 and ia64 initialize _PDC with mostly common bit settings. Factor out the common settings and leave the arch-specific ones alone. Cc: Tony Luck <tony.luck@intel.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Signed-off-by: NAlex Chiang <achiang@hp.com> Signed-off-by: NLen Brown <len.brown@intel.com>
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由 Alex Chiang 提交于
The x86 and ia64 implementations of arch_acpi_processor_init_pdc() are almost exactly the same. The only difference is in what bits they set in obj_list buffer. Combine the boilerplate memory management code, and leave the arch-specific bit twiddling in separate implementations. Cc: Tony Luck <tony.luck@intel.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Signed-off-by: NAlex Chiang <achiang@hp.com> Signed-off-by: NLen Brown <len.brown@intel.com>
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由 Alex Chiang 提交于
arch dependent helper function that tells us if we should attempt to evaluate _PDC on this machine or not. The x86 implementation assumes that the CPUs in the machine must be homogeneous, and that you cannot mix CPUs of different vendors. Cc: Tony Luck <tony.luck@intel.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Signed-off-by: NAlex Chiang <achiang@hp.com> Signed-off-by: NLen Brown <len.brown@intel.com>
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- 21 12月, 2009 4 次提交
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由 Paul Mundt 提交于
We don't actually require this in the cpu_relax() polling case, so just cuddle these around the sleeping version. Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Paul Mundt 提交于
This fixes up some crashes with IRQs racing the need_resched() test under QEMU. Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Albert Herranz 提交于
Fix the following build failures: arch/powerpc/platforms/embedded6xx/flipper-pic.c: In function 'flipper_pic_map': arch/powerpc/platforms/embedded6xx/flipper-pic.c:105: error: implicit declaration of function 'get_irq_desc' arch/powerpc/platforms/embedded6xx/hlwd-pic.c: In function 'hlwd_pic_map': arch/powerpc/platforms/embedded6xx/hlwd-pic.c:98: error: implicit declaration of function 'get_irq_desc' These failures are caused by the changes introduced in commit "powerpc: Remove get_irq_desc()". The reason these drivers were not updated is that they weren't merged yet. Signed-off-by: NAlbert Herranz <albert_herranz@yahoo.es> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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由 Albert Herranz 提交于
Fix the following build failures: arch/powerpc/platforms/embedded6xx/hlwd-pic.c: In function 'hlwd_pic_irq_cascade': arch/powerpc/platforms/embedded6xx/hlwd-pic.c:135: error: passing argument 1 of 'spin_lock' from incompatible pointer type arch/powerpc/platforms/embedded6xx/hlwd-pic.c:137: error: passing argument 1 of 'spin_unlock' from incompatible pointer type arch/powerpc/platforms/embedded6xx/hlwd-pic.c:145: error: passing argument 1 of 'spin_lock' from incompatible pointer type arch/powerpc/platforms/embedded6xx/hlwd-pic.c:149: error: passing argument 1 of 'spin_unlock' from incompatible pointer type These failures are caused by the changes introduced in commit "genirq: Convert irq_desc.lock to raw_spinlock". The reason this driver was not updated is that it wasn't merged yet. Signed-off-by: NAlbert Herranz <albert_herranz@yahoo.es> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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- 19 12月, 2009 6 次提交
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由 Heiko Carstens 提交于
Cc: Michael Holzheu <holzheu@linux.vnet.ibm.com> Signed-off-by: NHeiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>
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由 Oleg Nesterov 提交于
Nobody except ptrace itself should use task->ptrace or PT_PTRACED directly, change arch/s390/kernel/traps.c to use the helper. Signed-off-by: NOleg Nesterov <oleg@redhat.com> Acked-by: NRoland McGrath <roland@redhat.com> Signed-off-by: NHeiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>
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由 Martin Schwidefsky 提交于
The elf notes number for the upper register halves is s390 specific. Change the name of the elf notes to include S390. Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com> Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>
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由 Roel Kluin 提交于
Return the PTR_ERR of the correct pointer. Signed-off-by: NRoel Kluin <roel.kluin@gmail.com> Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>
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由 Heiko Carstens 提交于
Signed-off-by: NHeiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>
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由 Russell King 提交于
26-bit ARM support was removed a long time ago, and this symbol has been defined to be 'y' ever since. As it's never disabled anymore, we can kill it without any side effects. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 18 12月, 2009 1 次提交
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由 Russell King 提交于
This avoids races in the VFP code where the dead thread may have state on another CPU. By moving this code to exit_thread(), we will be running as the thread, and therefore be running on the current CPU. This means that we can ensure that the only local state is accessed in the thread notifiers. Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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