The clocks on the Arria 10 platform is a bit different than the
Cyclone/Arria 5 platform that it should just have it's own
driver.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

commit [1771b10d clk: respect the clock dependencies in of_clk_init]
exposed a flaw in the socfpga clock driver and prevents the platform
from booting on 3.15-rc1.

Because the "altr,clk-mgr" is not really a clock, it should not be using
CLK_OF_DECLARE, instead we should be mapping the clk-mgr's base address
one of the functional clock init function. Use the socfpga_pll_init function
to map the clk_mgr_base_addr as this clock should always be initialized first.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Tested-by: NPavel Machek <pavel@denx.de>

The PLLs can be from 3 different sources: osc1, osc2, or the f2s_ref_clk.
Update the clock driver to be able to get the correct parent.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Use 64-bit integer for calculating clock rate. Also use do_div for the
64-bit division.
Signed-off-by: NGraham Moore <grmoore@altera.com>
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Move the different kinds of clocks into their own files. The reason is to aid
readability of the code. This also goes along with the other SoC-specific
clock drivers.

The split introduces new structs for the three types of clocks and uses them.
Other changes are not done to the code.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>