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  1. 05 6月, 2015 1 次提交
  3. 06 5月, 2015 1 次提交
  5. 13 4月, 2015 1 次提交
  7. 22 1月, 2015 3 次提交
  9. 18 1月, 2015 1 次提交
  11. 01 1月, 2015 1 次提交
  13. 31 12月, 2014 1 次提交
    • D
      clk: rockchip: rk3288: Make s2r reliable by switching PLLs to slow mode · a7d95000
      由 Doug Anderson 提交于 
      We've been seeing some crashes at resume time on rk3288-based systems.
On some machines they simply never wake up from suspend.  Symptoms
include:

- System clearly got to sleep OK.  Power consumption is low, the PWM
  for the PWM regulator has stopped, and the "global_pwroff" output
  shows that the system is down.

- When system tries to wake up power consumption goes up.

- No kernel resume code (which was left in PMU SRAM) ran.  We added
  some basic logging to this code (write to a location in SRAM right
  at resume time) and didn't see the logging run.

It appears that we can fix the problem by slowing down APLL before we
suspend.  On the system I tested things seemed reliable if I disabled
1.8GHz and 1.7GHz.  The Mask ROM itself tries to slow things down
(which is why PLLs are in slow mode by the time we get to the kernel),
but apparently it is crashing before it even gets there.

We'll be super paranoid and not just go down to 1.6GHz but we'll match
what the Mask ROM seems to be doing and go into slow mode.  We'll also
be safe and put all PLLs (not just APLL) into slow mode (well, except
DPLL which is needed for SDRAM).  We'll even put NPLL into slow mode
which the Mask ROM didn't do (not that it's used for much important
stuff at early resume time).

Note that the old Rockchip reference code did something just like
this, though they jammed it into pm.c instead of putting it in the
syscore ops of the clock driver.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
      a7d95000
  15. 29 12月, 2014 2 次提交
    • H
      clk: rockchip: fix rk3288 cpuclk core dividers · 9880d427
      由 Heiko Stuebner 提交于 
      Commit 0e5bdb3f (clk: rockchip: switch to using the new cpuclk type
for armclk) didn't take into account that the divider used on rk3288
are of the (n+1) type.

The rk3066 and rk3188 socs use more complex divider types making it
necessary for the list-elements to be the real register-values to write.

Therefore reduce divider values in the table accordingly so that they
really are the values that should be written to the registers and match
the dividers actually specified for the rk3288.
Reported-by: NSonny Rao <sonnyrao@chromium.org>
Fixes: 0e5bdb3f ("clk: rockchip: switch to using the new cpuclk type for armclk")
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Cc: stable@vger.kernel.org
      9880d427
    • H
      clk: rockchip: fix rk3066 pll lock bit location · 12551f02
      由 Heiko Stuebner 提交于 
      The bit locations indicating the locking status of the plls on rk3066 are
shifted by one to the right when compared to the rk3188, bits [7:4] instead
of [8:5] on the rk3188, thus indicating the locking state of the wrong pll
or a completely different information in case of the gpll.

The recently introduced pll init code exposed that problem on some rk3066
boards when it tried to bring the boot-pll value in line with the value
from the rate table.

Fix this by defining separate pll definitions for rk3066 with the correct
locking indices.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Fixes: 2c14736c ("clk: rockchip: add clock driver for rk3188 and rk3066 clocks")
Tested-by: NFUKAUMI Naoki <naobsd@gmail.com>
Cc: stable@vger.kernel.org
      12551f02
  17. 21 12月, 2014 3 次提交
  19. 28 11月, 2014 2 次提交
  21. 27 11月, 2014 1 次提交
  23. 25 11月, 2014 4 次提交
  25. 23 11月, 2014 2 次提交
  27. 18 11月, 2014 2 次提交
    • J
      clk: rockchip: fix parent clock for rk3188 hclk_lcdc1 · f0c71718
      由 Julien CHAUVEAU 提交于 
      The parent clock for hclk_lcdc1 was set to aclk_cpu instead of hclk_cpu.
Signed-off-by: NJulien CHAUVEAU <julien.chauveau@neo-technologies.fr>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
      f0c71718
    • J
      clk-divider: Fix READ_ONLY when divider > 1 · e6d5e7d9
      由 James Hogan 提交于 
      Commit 79c6ab50 (clk: divider: add CLK_DIVIDER_READ_ONLY flag) in
v3.16 introduced the CLK_DIVIDER_READ_ONLY flag which caused the
recalc_rate() and round_rate() clock callbacks to be omitted.

However using this flag has the unfortunate side effect of causing the
clock recalculation code when a clock rate change is attempted to always
treat it as a pass-through clock, i.e. with a fixed divide of 1, which
may not be the case. Child clock rates are then recalculated using the
wrong parent rate.

Therefore instead of dropping the recalc_rate() and round_rate()
callbacks, alter clk_divider_bestdiv() to always report the current
divider as the best divider so that it is never altered.

For me the read only clock was the system clock, which divided the PLL
rate by 2, from which both the UART and the SPI clocks were divided.
Initial setting of the UART rate set it correctly, but when the SPI
clock was set, the other child clocks were miscalculated. The UART clock
was recalculated using the PLL rate as the parent rate, resulting in a
UART new_rate of double what it should be, and a UART which spewed forth
garbage when the rate changes were propagated.
Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Cc: Tomasz Figa <t.figa@samsung.com>
Cc: Max Schwarz <max.schwarz@online.de>
Cc: <stable@vger.kernel.org> # v3.16+
Acked-by: NHaojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>
      e6d5e7d9
  29. 16 11月, 2014 2 次提交
  31. 13 11月, 2014 1 次提交
  33. 11 11月, 2014 1 次提交
  35. 08 11月, 2014 1 次提交
  37. 05 11月, 2014 1 次提交
  39. 30 10月, 2014 1 次提交
    • K
      clk: rockchip: change PLL setting for better clock jitter · 49ed9ee4
      由 Kever Yang 提交于 
      dclk_vop0/1 is the source of HDMI TMDS clock in rk3288, usually we
use 594MHz for clock source of dclk_vop0/1.

HDMI CTS 7-9 require TMDS Clock jitter is lower than 0.25*Tbit:
TMDS clock(MHz)		CTS require jitter (ps)
	297		84.2
	148.5		168
	74.25		336
	27		1247

PLL BW and VCO frequency effects the jitter of PLL output clock,
clock jitter is better if BW is lower or VCO frequency is higher.

If PLL use default setting of RK3066_PLL_RATE( 594000000, 2, 198, 4),
the TMDS Clock jitter is higher than 250ps, which means we can't
pass the test when TMDS clock is 297MHz or 148.5MHz.

If we use RK3066_PLL_RATE_BWADJ(594000000, 1, 198, 8, 1),
the TMDS Clock jitter is about 60ps and we can pass all test case.

So we need this patch to make hdmi si test pass.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
      49ed9ee4
  41. 20 10月, 2014 5 次提交
  43. 01 10月, 2014 2 次提交
  45. 27 9月, 2014 1 次提交