1. 19 9月, 2016 1 次提交
  2. 02 8月, 2016 1 次提交
    • P
      MIPS: Use per-mm page to execute branch delay slot instructions · 432c6bac
      Paul Burton 提交于
      In some cases the kernel needs to execute an instruction from the delay
      slot of an emulated branch instruction. These cases include:
      
        - Emulated floating point branch instructions (bc1[ft]l?) for systems
          which don't include an FPU, or upon which the kernel is run with the
          "nofpu" parameter.
      
        - MIPSr6 systems running binaries targeting older revisions of the
          architecture, which may include branch instructions whose encodings
          are no longer valid in MIPSr6.
      
      Executing instructions from such delay slots is done by writing the
      instruction to memory followed by a trap, as part of an "emuframe", and
      executing it. This avoids the requirement of an emulator for the entire
      MIPS instruction set. Prior to this patch such emuframes are written to
      the user stack and executed from there.
      
      This patch moves FP branch delay emuframes off of the user stack and
      into a per-mm page. Allocating a page per-mm leaves userland with access
      to only what it had access to previously, and compared to other
      solutions is relatively simple.
      
      When a thread requires a delay slot emulation, it is allocated a frame.
      A thread may only have one frame allocated at any one time, since it may
      only ever be executing one instruction at any one time. In order to
      ensure that we can free up allocated frame later, its index is recorded
      in struct thread_struct. In the typical case, after executing the delay
      slot instruction we'll execute a break instruction with the BRK_MEMU
      code. This traps back to the kernel & leads to a call to do_dsemulret
      which frees the allocated frame & moves the user PC back to the
      instruction that would have executed following the emulated branch.
      In some cases the delay slot instruction may be invalid, such as a
      branch, or may trigger an exception. In these cases the BRK_MEMU break
      instruction will not be hit. In order to ensure that frames are freed
      this patch introduces dsemul_thread_cleanup() and calls it to free any
      allocated frame upon thread exit. If the instruction generated an
      exception & leads to a signal being delivered to the thread, or indeed
      if a signal simply happens to be delivered to the thread whilst it is
      executing from the struct emuframe, then we need to take care to exit
      the frame appropriately. This is done by either rolling back the user PC
      to the branch or advancing it to the continuation PC prior to signal
      delivery, using dsemul_thread_rollback(). If this were not done then a
      sigreturn would return to the struct emuframe, and if that frame had
      meanwhile been used in response to an emulated branch instruction within
      the signal handler then we would execute the wrong user code.
      
      Whilst a user could theoretically place something like a compact branch
      to self in a delay slot and cause their thread to become stuck in an
      infinite loop with the frame never being deallocated, this would:
      
        - Only affect the users single process.
      
        - Be architecturally invalid since there would be a branch in the
          delay slot, which is forbidden.
      
        - Be extremely unlikely to happen by mistake, and provide a program
          with no more ability to harm the system than a simple infinite loop
          would.
      
      If a thread requires a delay slot emulation & no frame is available to
      it (ie. the process has enough other threads that all frames are
      currently in use) then the thread joins a waitqueue. It will sleep until
      a frame is freed by another thread in the process.
      
      Since we now know whether a thread has an allocated frame due to our
      tracking of its index, the cookie field of struct emuframe is removed as
      we can be more certain whether we have a valid frame. Since a thread may
      only ever have a single frame at any given time, the epc field of struct
      emuframe is also removed & the PC to continue from is instead stored in
      struct thread_struct. Together these changes simplify & shrink struct
      emuframe somewhat, allowing twice as many frames to fit into the page
      allocated for them.
      
      The primary benefit of this patch is that we are now free to mark the
      user stack non-executable where that is possible.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com>
      Cc: Maciej Rozycki <maciej.rozycki@imgtec.com>
      Cc: Faraz Shahbazker <faraz.shahbazker@imgtec.com>
      Cc: Raghu Gandham <raghu.gandham@imgtec.com>
      Cc: Matthew Fortune <matthew.fortune@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/13764/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      432c6bac
  3. 28 5月, 2016 1 次提交
  4. 21 5月, 2016 1 次提交
    • J
      exit_thread: remove empty bodies · 5f56a5df
      Jiri Slaby 提交于
      Define HAVE_EXIT_THREAD for archs which want to do something in
      exit_thread. For others, let's define exit_thread as an empty inline.
      
      This is a cleanup before we change the prototype of exit_thread to
      accept a task parameter.
      
      [akpm@linux-foundation.org: fix mips]
      Signed-off-by: NJiri Slaby <jslaby@suse.cz>
      Cc: "David S. Miller" <davem@davemloft.net>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Cc: "James E.J. Bottomley" <jejb@parisc-linux.org>
      Cc: Aurelien Jacquiot <a-jacquiot@ti.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Chen Liqin <liqin.linux@gmail.com>
      Cc: Chris Metcalf <cmetcalf@mellanox.com>
      Cc: Chris Zankel <chris@zankel.net>
      Cc: David Howells <dhowells@redhat.com>
      Cc: Fenghua Yu <fenghua.yu@intel.com>
      Cc: Geert Uytterhoeven <geert@linux-m68k.org>
      Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
      Cc: Haavard Skinnemoen <hskinnemoen@gmail.com>
      Cc: Hans-Christian Egtvedt <egtvedt@samfundet.no>
      Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
      Cc: Helge Deller <deller@gmx.de>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: Jeff Dike <jdike@addtoit.com>
      Cc: Jesper Nilsson <jesper.nilsson@axis.com>
      Cc: Jiri Slaby <jslaby@suse.cz>
      Cc: Jonas Bonn <jonas@southpole.se>
      Cc: Koichi Yasutake <yasutake.koichi@jp.panasonic.com>
      Cc: Lennox Wu <lennox.wu@gmail.com>
      Cc: Ley Foon Tan <lftan@altera.com>
      Cc: Mark Salter <msalter@redhat.com>
      Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
      Cc: Matt Turner <mattst88@gmail.com>
      Cc: Max Filippov <jcmvbkbc@gmail.com>
      Cc: Michael Ellerman <mpe@ellerman.id.au>
      Cc: Michal Simek <monstr@monstr.eu>
      Cc: Mikael Starvik <starvik@axis.com>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Rich Felker <dalias@libc.org>
      Cc: Richard Henderson <rth@twiddle.net>
      Cc: Richard Kuo <rkuo@codeaurora.org>
      Cc: Richard Weinberger <richard@nod.at>
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Steven Miao <realmz6@gmail.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Tony Luck <tony.luck@intel.com>
      Cc: Vineet Gupta <vgupta@synopsys.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      5f56a5df
  5. 13 5月, 2016 3 次提交
    • P
      MIPS: Force CPUs to lose FP context during mode switches · 6b832257
      Paul Burton 提交于
      Commit 9791554b ("MIPS,prctl: add PR_[GS]ET_FP_MODE prctl options
      for MIPS") added support for the PR_SET_FP_MODE prctl, which allows a
      userland program to modify its FP mode at runtime. This is most notably
      required if dynamic linking leads to the FP mode requirement changing at
      runtime from that indicated in the initial executable's ELF header. In
      order to avoid overhead in the general FP context restore code, it aimed
      to have threads in the process become unable to enable the FPU during a
      mode switch & have the thread calling the prctl syscall wait for all
      other threads in the process to be context switched at least once. Once
      that happens we can know that no thread in the process whose mode will
      be switched has live FP context, and it's safe to perform the mode
      switch. However in the (rare) case of modeswitches occurring in
      multithreaded programs this can lead to indeterminate delays for the
      thread invoking the prctl syscall, and the code monitoring for those
      context switches was woefully inadequate for all but the simplest cases.
      
      Fix this by broadcasting an IPI if other CPUs may have live FP context
      for an affected thread, with a handler causing those CPUs to relinquish
      their FPU ownership. Threads will then be allowed to continue running
      but will stall on the wait_on_atomic_t in enable_restore_fp_context if
      they attempt to use FP again whilst the mode switch is still in
      progress. The end result is less fragile poking at scheduler context
      switch counts & a more expedient completion of the mode switch.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Fixes: 9791554b ("MIPS,prctl: add PR_[GS]ET_FP_MODE prctl options for MIPS")
      Reviewed-by: NMaciej W. Rozycki <macro@imgtec.com>
      Cc: Adam Buchbinder <adam.buchbinder@gmail.com>
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: stable <stable@vger.kernel.org> # v4.0+
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/13145/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      6b832257
    • P
      MIPS: Disable preemption during prctl(PR_SET_FP_MODE, ...) · bd239f1e
      Paul Burton 提交于
      Whilst a PR_SET_FP_MODE prctl is performed there are decisions made
      based upon whether the task is executing on the current CPU. This may
      change if we're preempted, so disable preemption to avoid such changes
      for the lifetime of the mode switch.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Fixes: 9791554b ("MIPS,prctl: add PR_[GS]ET_FP_MODE prctl options for MIPS")
      Reviewed-by: NMaciej W. Rozycki <macro@imgtec.com>
      Tested-by: NAurelien Jarno <aurelien@aurel32.net>
      Cc: Adam Buchbinder <adam.buchbinder@gmail.com>
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: stable <stable@vger.kernel.org> # v4.0+
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/13144/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      bd239f1e
    • R
      MIPS: Make flush_thread · 04cc89d1
      Ralf Baechle 提交于
      Avoids function calls to an empty function.
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      04cc89d1
  6. 09 5月, 2016 1 次提交
    • J
      MIPS: Don't unwind to user mode with EVA · a816b306
      James Hogan 提交于
      When unwinding through IRQs and exceptions, the unwinding only continues
      if the PC is a kernel text address, however since EVA it is possible for
      user and kernel address ranges to overlap, potentially allowing
      unwinding to continue to user mode if the user PC happens to be in the
      kernel text address range.
      
      Adjust the check to also ensure that the register state from before the
      exception is actually running in kernel mode, i.e. !user_mode(regs).
      
      I don't believe any harm can come of this problem, since the PC is only
      output, the stack pointer is checked to ensure it resides within the
      task's stack page before it is dereferenced in search of the return
      address, and the return address register is similarly only output (if
      the PC is in a leaf function or the beginning of a non-leaf function).
      
      However unwind_stack() is only meant for unwinding kernel code, so to be
      correct the unwind should stop there.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Reviewed-by: NLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: <stable@vger.kernel.org> # 3.15+
      Patchwork: https://patchwork.linux-mips.org/patch/11700/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      a816b306
  7. 03 4月, 2016 1 次提交
  8. 02 2月, 2016 1 次提交
  9. 24 3月, 2015 1 次提交
  10. 05 3月, 2015 1 次提交
  11. 17 2月, 2015 1 次提交
  12. 12 2月, 2015 1 次提交
    • P
      MIPS,prctl: add PR_[GS]ET_FP_MODE prctl options for MIPS · 9791554b
      Paul Burton 提交于
      Userland code may be built using an ABI which permits linking to objects
      that have more restrictive floating point requirements. For example,
      userland code may be built to target the O32 FPXX ABI. Such code may be
      linked with other FPXX code, or code built for either one of the more
      restrictive FP32 or FP64. When linking with more restrictive code, the
      overall requirement of the process becomes that of the more restrictive
      code. The kernel has no way to know in advance which mode the process
      will need to be executed in, and indeed it may need to change during
      execution. The dynamic loader is the only code which will know the
      overall required mode, and so it needs to have a means to instruct the
      kernel to switch the FP mode of the process.
      
      This patch introduces 2 new options to the prctl syscall which provide
      such a capability. The FP mode of the process is represented as a
      simple bitmask combining a number of mode bits mirroring those present
      in the hardware. Userland can either retrieve the current FP mode of
      the process:
      
        mode = prctl(PR_GET_FP_MODE);
      
      or modify the current FP mode of the process:
      
        err = prctl(PR_SET_FP_MODE, new_mode);
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Cc: Matthew Fortune <matthew.fortune@imgtec.com>
      Cc: Markos Chandras <markos.chandras@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/8899/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      9791554b
  13. 31 1月, 2015 1 次提交
    • J
      MIPS: fork: Fix MSA/FPU/DSP context duplication race · 39148e94
      James Hogan 提交于
      There is a race in the MIPS fork code which allows the child to get a
      stale copy of parent MSA/FPU/DSP state that is active in hardware
      registers when the fork() is called. This is because copy_thread() saves
      the live register state into the child context only if the hardware is
      currently in use, apparently on the assumption that the hardware state
      cannot have been saved and disabled since the initial duplication of the
      task_struct. However preemption is certainly possible during this
      window.
      
      An example sequence of events is as follows:
      
      1) The parent userland process puts important data into saved floating
         point registers ($f20-$f31), which are then dirty compared to the
         process' stored context.
      
      2) The parent process calls fork() which does a clone system call.
      
      3) In the kernel, do_fork() -> copy_process() -> dup_task_struct() ->
         arch_dup_task_struct() (which uses the weakly defined default
         implementation). This duplicates the parent process' task context,
         which includes a stale version of its FP context from when it was
         last saved, probably some time before (1).
      
      4) At some point before copy_process() calls copy_thread(), such as when
         duplicating the memory map, the process is desceduled. Perhaps it is
         preempted asynchronously, or perhaps it sleeps while blocked on a
         mutex. The dirty FP state in the FP registers is saved to the parent
         process' context and the FPU is disabled.
      
      5) When the process is rescheduled again it continues copying state
         until it gets to copy_thread(), which checks whether the FPU is in
         use, so that it can copy that dirty state to the child process' task
         context. Because of the deschedule however the FPU is not in use, so
         the child process' context is left with stale FP context from the
         last time the parent saved it (some time before (1)).
      
      6) When the new child process is scheduled it reads the important data
         from the saved floating point register, and ends up doing a NULL
         pointer dereference as a result of the stale data.
      
      This use of saved floating point registers across function calls can be
      triggered fairly easily by explicitly using inline asm with a current
      (MIPS R2) compiler, but is far more likely to happen unintentionally
      with a MIPS R6 compiler where the FP registers are more likely to get
      used as scratch registers for storing non-fp data.
      
      It is easily fixed, in the same way that other architectures do it, by
      overriding the implementation of arch_dup_task_struct() to sync the
      dirty hardware state to the parent process' task context *prior* to
      duplicating it, rather than copying straight to the child process' task
      context in copy_thread(). Note, the FPU hardware is not disabled so the
      parent process may continue executing with the live register context,
      but now the child process is guaranteed to have an identical copy of it
      at that point.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Reported-by: NMatthew Fortune <matthew.fortune@imgtec.com>
      Tested-by: NMarkos Chandras <markos.chandras@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/9075/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      39148e94
  14. 24 11月, 2014 2 次提交
    • E
      MIPS: Add arch_trigger_all_cpu_backtrace() function · 856839b7
      Eunbong Song 提交于
      Currently, arch_trigger_all_cpu_backtrace() is defined in only x86 and
      sparc which have an NMI.  But in case of softlockup, it could be possible
      to dump backtrace of all cpus. and this could be helpful for debugging.
      
      for example, if system has 2 cpus.
      
      	CPU 0				CPU 1
       acquire read_lock()
      
      				try to do write_lock()
      
       ,,,
       missing read_unlock()
      
      In this case, softlockup will occur becasuse CPU 0 does not call
      read_unlock().  And dump_stack() print only backtrace for "CPU 0". If
      CPU1's backtrace is printed it's very helpful.
      
      [ralf@linux-mips.org: Fixed whitespace and formatting issues.]
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/8200/
      856839b7
    • R
      MIPS: Remove useless parentheses · 635c9907
      Ralf Baechle 提交于
      Based on the spatch
      
      @@
      expression e;
      @@
      - return (e);
      + return e;
      
      with heavy hand editing because some of the changes are either whitespace
      or identation only or result in excessivly long lines.
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      635c9907
  15. 02 8月, 2014 3 次提交
  16. 24 5月, 2014 1 次提交
    • R
      MIPS: MT: Remove SMTC support · b633648c
      Ralf Baechle 提交于
      Nobody is maintaining SMTC anymore and there also seems to be no userbase.
      Which is a pity - the SMTC technology primarily developed by Kevin D.
      Kissell <kevink@paralogos.com> is an ingenious demonstration for the MT
      ASE's power and elegance.
      
      Based on Markos Chandras <Markos.Chandras@imgtec.com> patch
      https://patchwork.linux-mips.org/patch/6719/ which while very similar did
      no longer apply cleanly when I tried to merge it plus some additional
      post-SMTC cleanup - SMTC was a feature as tricky to remove as it was to
      merge once upon a time.
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      b633648c
  17. 27 3月, 2014 2 次提交
    • P
      MIPS: Basic MSA context switching support · 1db1af84
      Paul Burton 提交于
      This patch adds support for context switching the MSA vector registers.
      These 128 bit vector registers are aliased with the FP registers - an
      FP register accesses the least significant bits of the vector register
      with which it is aliased (ie. the register with the same index). Due to
      both this & the requirement that the scalar FPU must be 64-bit (FR=1) if
      enabled at the same time as MSA the kernel will enable MSA & scalar FP
      at the same time for tasks which use MSA. If we restore the MSA vector
      context then we might as well enable the scalar FPU since the reason it
      was left disabled was to allow for lazy FP context restoring - but we
      just restored the FP context as it's a subset of the vector context. If
      we restore the FP context and have previously used MSA then we have to
      restore the whole vector context anyway (see comment in
      enable_restore_fp_context for details) so similarly we might as well
      enable MSA.
      
      Thus if a task does not use MSA then it will continue to behave as
      without this patch - the scalar FP context will be saved & restored as
      usual. But if a task executes an MSA instruction then it will save &
      restore the vector context forever more.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/6431/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      1db1af84
    • P
      MIPS: Don't assume 64-bit FP registers for dump_{,task_}fpu · 6cec7c4a
      Paul Burton 提交于
      This code assumed that saved FP registers are 64 bits wide, an
      assumption which will no longer be true once MSA is introduced. This
      patch modifies the code to copy the lower 64 bits of each register in
      turn, which is safe for any FP register width >= 64 bits.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/6425/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      6cec7c4a
  18. 25 1月, 2014 1 次提交
  19. 14 1月, 2014 1 次提交
    • P
      MIPS: Support for 64-bit FP with O32 binaries · 597ce172
      Paul Burton 提交于
      CPUs implementing MIPS32 R2 may include a 64-bit FPU, just as MIPS64 CPUs
      do. In order to preserve backwards compatibility a 64-bit FPU will act
      like a 32-bit FPU (by accessing doubles from the least significant 32
      bits of an even-odd pair of FP registers) when the Status.FR bit is
      zero, again just like a mips64 CPU. The standard O32 ABI is defined
      expecting a 32-bit FPU, however recent toolchains support use of a
      64-bit FPU from an O32 MIPS32 executable. When an ELF executable is
      built to use a 64-bit FPU a new flag (EF_MIPS_FP64) is set in the ELF
      header.
      
      With this patch the kernel will check the EF_MIPS_FP64 flag when
      executing an O32 binary, and set Status.FR accordingly. The addition
      of O32 64-bit FP support lessens the opportunity for optimisation in
      the FPU emulator, so a CONFIG_MIPS_O32_FP64_SUPPORT Kconfig option is
      introduced to allow this support to be disabled for those that don't
      require it.
      
      Inspired by an earlier patch by Leonid Yegoshin, but implemented more
      cleanly & correctly.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: Paul Burton <paul.burton@imgtec.com>
      Patchwork: https://patchwork.linux-mips.org/patch/6154/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      597ce172
  20. 01 7月, 2013 2 次提交
  21. 22 5月, 2013 1 次提交
  22. 18 5月, 2013 2 次提交
    • T
      MIPS: Extract schedule_mfi info from __schedule · 5000653e
      Tony Wu 提交于
      schedule_mfi is supposed to be extracted from schedule(), and
      is used in thread_saved_pc and get_wchan.
      
      But, after optimization, schedule() is reduced to a sibling
      call to __schedule(), and no real frame info can be extracted.
      
      One solution is to compile schedule() with -fno-omit-frame-pointer
      and -fno-optimize-sibling-calls, but that will incur performance
      degradation.
      
      Another solution is to extract info from the real scheduler,
      __schedule, and this is the approache adopted here.
      
      This patch reads the __schedule address by either following
      the 'j' call in schedule if KALLSYMS is disabled or by using
      kallsyms_lookup_name to lookup __schedule if KALLSYMS is
      available, then, extracts schedule_mfi from __schedule frame info.
      
      This patch also fixes the "Can't analyze schedule() prologue"
      warning at boot time.
      Signed-off-by: NTony Wu <tung7970@gmail.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/5237/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      5000653e
    • T
      MIPS: Fix sibling call handling in get_frame_info · e7438c4b
      Tony Wu 提交于
      Given a function, get_frame_info() analyzes its instructions
      to figure out frame size and return address. get_frame_info()
      works as follows:
      
      1. analyze up to 128 instructions if the function size is unknown
      2. search for 'addiu/daddiu sp,sp,-immed' for frame size
      3. search for 'sw ra,offset(sp)' for return address
      4. end search when it sees jr/jal/jalr
      
      This leads to an issue when the given function is a sibling
      call, example shown as follows.
      
      801ca110 <schedule>:
      801ca110:       8f820000        lw      v0,0(gp)
      801ca114:       8c420000        lw      v0,0(v0)
      801ca118:       080726f0        j       801c9bc0 <__schedule>
      801ca11c:       00000000        nop
      
      801ca120 <io_schedule>:
      801ca120:       27bdffe8        addiu   sp,sp,-24
      801ca124:       3c028022        lui     v0,0x8022
      801ca128:       afbf0014        sw      ra,20(sp)
      
      In this case, get_frame_info() cannot properly detect schedule's
      frame info, and eventually returns io_schedule's instead.
      
      This patch adds 'j' to the end search condition to workaround
      sibling call cases.
      Signed-off-by: NTony Wu <tung7970@gmail.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/5236/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      e7438c4b
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