The socfpga.dtsi currently has the wrong interrupt number set for SPI master 1
Trying to use the master without this change results in the kernel boot
process waiting forever for an interrupt that will never occur while
attempting to probe any slave devices configured in the device tree as being
under SPI master 1.

The change works for the Cyclone V, and according to the Arria 5 handbook
should be good there too.
Signed-off-by: NMark James <maj@jamers.net>
Acked-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>

Commit 7800064b ("ARM: dts: Add basic dm816x device tree
configuration") added basic devices for dm816x, but I was not able
to test the GPIO interrupts earlier until I found some suitable pins
to test with. We can mux the MMC card detect and write protect pins
from SD_SDCD and SD_SDWP mode to use a normal GPIO interrupts that
are also suitable for the MMC subsystem.

This turned out several issues that need to be fixed:

- I set the GPIO type wrong to be compatible with omap3 instead
  of omap4. The GPIO controller on dm816x has EOI interrupt
  register like omap4 and am335x.

- I got the GPIO interrupt numbers wrong as each bank has two
  and we only use one. They need to be set up the same way as
  on am335x.

- The gpio banks are missing interrupt controller related
  properties.

With these changes the GPIO interrupts can be used with the
MMC card detect pin, so let's wire that up. Let's also mux all
the MMC lines for completeness while at it.

For the first GPIO bank I tested using GPMC lines temporarily
muxed to GPIOs on the dip switch 10.

Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Now that we don't have hwmod entry for pcie PHY remove the
ti,hwmod property from PCIE PHY's. Otherwise we will get:

platform 4a094000.pciephy: Cannot lookup hwmod 'pcie1-phy'
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
[tony@atomide.com: updated comments]
Signed-off-by: NTony Lindgren <tony@atomide.com>

This patch adds missing dma DTS definitions for omap aes and sham drivers.
Without it kernel drivers do not work for device tree based booting
while it works for legacy booting on general purpose SoCs.

Note that further changes are still needed for high secure SoCs. But since
that never worked in legacy boot mode either, those will be sent separately.
Signed-off-by: NPali Rohár <pali.rohar@gmail.com>
Acked-by: NPavel  Machek <pavel@ucw.cz>
[tony@atomide.com: updated comments]
Signed-off-by: NTony Lindgren <tony@atomide.com>

This block should not be enabled by default or else if the kconfig is set,
it will try to load/probe even if there's no phy connected.
Signed-off-by: NAlexandru M Stan <amstan@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The UTMI clock must be selected by any high-speed USB IP. The logic behind it
needs this particular clock.
So, correct the clock in the device tree files affected.
Reported-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Cc: <stable@vger.kernel.org> #3.18

The at91rm9200, at91sam9260, at91sam9261 and at91sam9263 SoCs have slightly
different UDC IPs.
Those differences were previously handled with cpu_is_at91xx macro which
are about to be dropped for multi-platform support, thus we need to
change compatible strings.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

There is no specific driver handling the AHB matrix, this is a simple syscon
device. the matrix is needed by several other drivers including the USB on some
SoCs (at91sam9261 for instance).
Without this definition, the USB will not work on these SoCs.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

USB vbus 5V is from PMIC SWBST, so set swbst_reg as vbus's
parent reg, it fixed a bug that the voltage of vbus is incorrect
due to swbst_reg is disabled after boots up.

Cc: stable@vger.kernel.org
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

USB vbus 5V is from PMIC SWBST, so set swbst_reg as vbus's
parent reg, it fixed a bug that the voltage of vbus is incorrect
due to swbst_reg is disabled after boots up.

Cc: stable@vger.kernel.org
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Peripheral clock is named pclk and system clock is named hclk (those are
the names expected by the at91_udc driver).

Drop the deprecated usb_clk (formerly used to configure the usb clock rate
which is now directly configurable through hclk).
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

DCAN1 RX and TX lines are internally pulled high according to [1].
While muxing between DCAN mode and SAFE mode we make sure
that the same pull direction is set to minimize opposite
pull contention during the switching window.

[1] in DRA7 data manual, Ball characteristics table 4-2, DSIS colum shows
the state driven to the peripheral input while in the deselcted mode.
DSIS - De-Selected Input State.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Rev.F onwards ball G19 (dcan1_rx) is used as a GPIO for some other
function so don't include it in DCAN pinctrl node.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

OMAP4 has a finer counter granularity, which allows for a delay of 1000ms
in the thermal zone polling intervals. OMAP5 has a different counter
mechanism, which allows at maximum a 500ms timer. Adjust the cpu thermal
zone polling interval accordingly.

Without this patch, the polling interval information is simply ignored,
and the following thermal warnings are printed during boot (assuming
thermal is enabled);

[    1.545343] ti-soc-thermal 4a0021e0.bandgap: Delay 1000 ms is not supported
[    1.552691] ti-soc-thermal 4a0021e0.bandgap: Delay 1000 ms is not supported
[    1.560029] ti-soc-thermal 4a0021e0.bandgap: Delay 1000 ms is not supported
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Acked-by: NEduardo Valentin <edubezval@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Use external clock for RMII since the internal clock doesn't meet the
jitter requirements.
Signed-off-by: NGeorge McCollister <george.mccollister@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Beaglebone Black doesn't have AES and SHAM enabled like the
original Beaglebone White dts. This breaks applications that
leverage the crypto blocks so fix this by enabling these nodes
in the am335x-bone-common.dtsi. With this change, enabling the
nodes in am335x-bone.dts is no longer required so remove them.
Signed-off-by: NMatt Porter <mporter@konsulko.com>
Acked-by: NRobert Nelson <robertcnelson@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

ehrpwm tbclk is wrongly modelled as deriving from dpll_per_m2_ck.
The TRM says tbclk is derived from SYSCLKOUT. SYSCLKOUT nothing but the
functional clock of pwmss (l4ls_gclk).
Fix this by changing source of ehrpwmx_tbclk to l4ls_gclk.

Fixes: 4da1c677 ("add tbclk data for ehrpwm")
Signed-off-by: NVignesh R <vigneshr@ti.com>
Acked-by: NTero Kristo <t-kristo@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

ehrpwm tbclk is wrongly modelled as deriving from dpll_per_m2_ck.
The TRM says tbclk is derived from SYSCLKOUT. SYSCLKOUT nothing but the
functional clock of pwmss (l4ls_gclk).
Fix this by changing source of ehrpwmx_tbclk to l4ls_gclk.

Fixes: 9e100eba: ("Fix ehrpwm tbclk data")
Signed-off-by: NVignesh R <vigneshr@ti.com>
Acked-by: NTero Kristo <t-kristo@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Fixes 85dc74e9 (ARM: dts: omap5 clock data)

On OMAP54xx, For DPLL_IVA, the ref clock(CLKINP) is connected to sys_clk1 and
the bypass input(CLKINPULOW) is connected to iva_dpll_hs_clk_div clock.
But the bypass input is not directly routed to bypass clkout instead
both CLKINP and CLKINPULOW are connected to bypass clkout via a mux.

This mux is controlled by the bit - CM_CLKSEL_DPLL_IVA[23]:DPLL_BYP_CLKSEL
and it's POR value is zero which selects the CLKINP as bypass clkout.
which means iva_dpll_hs_clk_div is not the bypass clock for dpll_iva_ck

Fix this by adding another mux clock as parent in bypass mode.

This design is common to most of the PLLs and the rest have only one bypass
clock. Below is a list of the DPLLs that need this fix:

DPLL_IVA,
DPLL_PER,
DPLL_USB and DPLL_CORE
Signed-off-by: NRavikumar Kattekola <rk@ti.com>
Acked-by: NTero Kristo <t-kristo@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Fixes: ee6c7507 (ARM: dts: dra7 clock data)

On DRA7x, For DPLL_IVA, the ref clock(CLKINP) is connected to sys_clk1 and
the bypass input(CLKINPULOW) is connected to iva_dpll_hs_clk_div clock.
But the bypass input is not directly routed to bypass clkout instead
both CLKINP and CLKINPULOW are connected to bypass clkout via a mux.

This mux is controlled by the bit - CM_CLKSEL_DPLL_IVA[23]:DPLL_BYP_CLKSEL
and it's POR value is zero which selects the CLKINP as bypass clkout.
which means iva_dpll_hs_clk_div is not the bypass clock for dpll_iva_ck

Fix this by adding another mux clock as parent in bypass mode.

This design is common to most of the PLLs and the rest have only one bypass
clock. Below is a list of the DPLLs that need this fix:

DPLL_IVA, DPLL_DDR,
DPLL_DSP, DPLL_EVE,
DPLL_GMAC, DPLL_PER,
DPLL_USB and DPLL_CORE
Signed-off-by: NRavikumar Kattekola <rk@ti.com>
Acked-by: NTero Kristo <t-kristo@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

lcdck takes mck (not smd) as its parent. It is also assigned id 3 and not 4.
Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
[nicolas.ferre@atmel.com: squashed 2 related patches]
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Rename lcd_clk into lcdc_clk to be consistent with sama5d3 clock
definitions.
Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

socfpga.dtsi is missing the DMA channels for the uart nodes.
This will produce the following errors:

	of_dma_request_slave_channel: dma-names property of node '/soc/serial0@ffc02000' missing or empty
	ttyS0 - failed to request DMA

Provide the correct DMA channels to fix this.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>

Since turning on idle-halt in commit fe46aa67 (ARM: at91/dt: add
sam9 watchdog default options to SoCs), SoCs compatible with at91sam9260-wdt
no longer reboot if the watchdog times out while the CPU is in idle state.
Removing the 'idle-halt' flag that was set by default fixes this.
Signed-off-by: NMichel Marti <mma@objectxp.com>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: NSylvain Rochet <sylvain.rochet@finsecur.com>
[nicolas.ferre@atmel.com: rework the commit message]
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Corrected pins used by usart3.
Signed-off-by: NJonas Andersson <jonas@microbit.se>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Commit ff04660e48b20 ("ARM: at91/dt: add SRAM nodes") used the same base
address for sram0 and sram1 leading to the following warning:
WARNING: CPU: 0 PID: 1 at fs/sysfs/dir.c:31 sysfs_warn_dup+0x50/0x70()
sysfs: cannot create duplicate filename '/devices/platform/300000.sram'
Fix the base address for sram1.
Signed-off-by: NAlexander Stein <alexanders83@web.de>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

The patch adds domain definition and references to it in appropriate devices.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
[mszyprow: rebased onto generic power domains dt bindings]
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Tested-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

Mixed block needs to control hdmi clock to properly perform power on/off
operation, so add 'hdmi' clock also to mixer nodes.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

This patch adds configuration of hw modules required to enable HDMI
support on Universal C210 board.
Signed-off-by: NTomasz Stanislawski <t.stanislaws@samsung.com>
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

This patch adds nodes specific to Exynos4412 based Odroid X/X2/U2/U3
boards required for enabling HDMI display.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

TV Mixer needs both TV and LCD0 domains enabled to be fully operational.
This dependency is modelled by making TV power domains a sub-domain of
LCD0 power domain.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

This patch adds entries for HDMI, Mixer and i2c with hdmi-phy modules
found in Exynos 4210 and 4x12 SoCs.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

Presented device tree bindings provide data already hardcoded in the
exynos_tmu_data.c file.
After this commit, it should be possible to reuse common thermal core
framework in Exynos SoCs.
Signed-off-by: NLukasz Majewski <l.majewski@samsung.com>
Acked-by: NEduardo Valentin <edubezval@gmail.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

This commit provides information about Exynos5440 device configuration.
Previously this information was available in exynos_tmu_data.c file.
Now it is available in the device tree.
Such approach allows reusing some common code for thermal.
Signed-off-by: NLukasz Majewski <l.majewski@samsung.com>
Acked-by: NEduardo Valentin <edubezval@gmail.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

Trip points corresponding to the one defined in the exynos_tmu_data.c
for Exynos4 have been included.
This thermal-zones attribute is afterwards reused for Exynos4210,
Exynos4412 and Exynos5250.
Signed-off-by: NLukasz Majewski <l.majewski@samsung.com>
Acked-by: NEduardo Valentin <edubezval@gmail.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

This code groups in one place default settings of trip points.
It is used in SoCs with multiple instances of TMU sensor.

Separate device tree file prevents from multiple copying of the
same data.
Signed-off-by: NLukasz Majewski <l.majewski@samsung.com>
Acked-by: NEduardo Valentin <edubezval@gmail.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

Exynos 4 and 5 family of SoCs uses almost identical TMU sensor to
measure the on chip temperature. For this reason it is possible to
group TMU configuration parameters in one dts file.
Signed-off-by: NLukasz Majewski <l.majewski@samsung.com>
Acked-by: NEduardo Valentin <edubezval@gmail.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

Presented patch aims to move data necessary for correct CPU cooling device
configuration from exynos_tmu_data.c to device tree.
Signed-off-by: NLukasz Majewski <l.majewski@samsung.com>
Acked-by: NEduardo Valentin <edubezval@gmail.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

This commit enables TMU IP block on the Exynos4412 Odroid based
devices such as Odroid U3.
Signed-off-by: NLukasz Majewski <l.majewski@samsung.com>
Acked-by: NEduardo Valentin <edubezval@gmail.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>