include/linux/dw_spi.h only includes driver internal data.  It doesn't
expose a platform_data configuration structure or similar (at least
nothing in-tree).  This patch moves the header into drivers/spi so
that the scope is limited to only the dw_spi_*.c driver files
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
Cc: Feng Tang <feng.tang@intel.com>
Cc: spi-devel-general@lists.sourceforge.net

I don't have the specs for this beast, but it looks a lot like the PXA
GPIO block. Though I bet it's the same IP and the driver should have
reused the PXA code.

Acknowleding the edge detect status after handling one or more gpio
interrupts looks wrong. We might lose an edge which came in while we
handled the previous one.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Acked-by: NAlek Du <alek.du@intel.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Use __ffs() to find the pending interrupt source instead of looping 32
times.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Cc: Feng Tang <feng.tang@intel.com>
Cc: Alek Du <alek.du@intel.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Convert to the new irq function names.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Cc: Feng Tang <feng.tang@intel.com>
Cc: Alek Du <alek.du@intel.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

commit 0766d20f (langwell_gpio: modify EOI handling following change
of kernel irq subsystem)  changes

 -   desc->chip->eoi(irq);
 +
 +   if (desc->chip->irq_eoi)
 +           desc->chip->irq_eoi(irq_get_irq_data(irq));
 +   else
 +           dev_warn(pg->chip.dev, "missing EOI handler for irq %d\n", irq);

With the following explanation:

 "Latest kernel has many changes in IRQ subsystem and its interfaces,
  like adding irq_eoi" for struct irq_chip, this patch will make it
  support both the new and old interface."

This is completely bogus.

 #1) The changelog does not match the patch at all

 #2) This driver relies on the assumption that it sits behind an eoi
     capable interrupt line. If the implementation of the underlying
     chip changes from eoi to irq_eoi then this driver has to follow
     that change and not add a total bogosity.

 #3) Just mechanically changing eoi to irq_eoi without checking the
     background of that change is sloppy at best.

Remove the sillyness and retrieve the interrupt data from irq_desc
directly. No need to go through a sparse irq lookup.
Reported-by: NStephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Cc: Feng Tang <feng.tang@intel.com>
Cc: Alek Du <alek.du@intel.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Cc: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Nothing outside of x86 can use that code.
Reported-by: NStephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Fix section mismatch by annotating using variable name suffix.
Signed-off-by: NNikanth Karthikesan <knikanth@suse.de>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The recently increased type checking in platform_get_drvdata() reveals a few
offenders:

drivers/rtc/rtc-ds1390.c:161: warning: passing argument 1 of ‘platform_get_drvdata’ from incompatible pointer type
drivers/rtc/rtc-ds3234.c:161: warning: passing argument 1 of ‘platform_get_drvdata’ from incompatible pointer type
drivers/rtc/rtc-m41t94.c:139: warning: passing argument 1 of ‘platform_get_drvdata’ from incompatible pointer type

Use spi_get_drvdata() instead of platform_get_drvdata().
Signed-off-by: NGeert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

In most cases, get_user_pages and get_user_pages_fast should be used
to pin user pages in memory.  But sometimes, some special flags except
FOLL_GET, FOLL_WRITE and FOLL_FORCE are needed, for example in
following patch, KVM needs FOLL_HWPOISON.  To support these users,
__get_user_pages is exported directly.

There are some symbol name conflicts in infiniband driver, fixed them too.
Signed-off-by: NHuang Ying <ying.huang@intel.com>
CC: Andrew Morton <akpm@linux-foundation.org>
CC: Michel Lespinasse <walken@google.com>
CC: Roland Dreier <roland@kernel.org>
CC: Ralph Campbell <infinipath@qlogic.com>
Signed-off-by: NMarcelo Tosatti <mtosatti@redhat.com>

Those should all be unsigned.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Fix amd64_debug_display_dimm_sizes() arguments order per convention (pvt
is always first). Also, the now second arg denotes the DCT so adjust its
type.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

The dram ranges make sense only as an unsigned type.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Use the macro directly instead
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Adjust argument types to the PCI config API's types.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Return unsigned u8 values only.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

A node id can never be negative since we use it as an index into
the DRAM ranges array. This also makes one of the BUG_ON conditions
redundant.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Those were moved to the mce_amd.h header.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Add the PCI device ids required for driver registration. Remove
pvt->ctl_name and use the family descriptor directly, instead. Then,
bump driver version and fixup its format. Finally, enable DRAM ECC
decoding on F15h.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

F15h has the same ECC symbol size options as F10h revD and later so
adjust checks to that. Simplify code a bit.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Drop per-instance variable and compute min scrubrate dynamically.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Drop static tables which map the bits in F2x80 to a chip select size in
favor of functions doing the mapping with some bit fiddling. Also, add
F15 support.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

This function is relevant for F10h and higher, and it has only one
callsite so drop its function pointer from the low_ops struct.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

F15h sys_addr to chip select mapping is almost identical to F10h's so
reuse that. Rename functions on that path accordingly.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Add paranoid checks for the sys address before going off and decoding
it.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Replace per-DCT macros with smarter ones, drop hack and look for the
spare rank on all chip selects on a channel.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Remove the channel interleave select bit properly. See
F2x110[DctSelIntLvAddr] for details.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

When node interleaving is enabled, a subset of the addr[14:12] bits has
to be removed in order to get the normalized DCT address of the DRAM
channel. The actual number of bits to remove is determined by F1x[1,
0][7C:40][IntlvEn]. Do this correctly.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

On revC3 and revE Fam10h machines and later, non-interleaved graphics
framebuffer memory under the 16G mark can be swapped with a region
located at the bottom of memory so that the GPU can use the interleaved
region and thus two channels. Add support for that.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

The address bits from MC4_STATUS differ only between K8 and the rest so
no need for a per-family method.

No functional change.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Use the struct mce directly instead of copying from it into a custom
struct err_regs.

No functionality change.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

The only difference is that F10h used to sport ganged DCTs and F15h
doesn't so adjust the F10h routine and reuse it.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Remove unused defines, drop family names from define names.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Remove reporting of errors with UC bit set - this is done by the MCE
decoding code anyway and this driver deals with DRAM ECC errors only. UC
(NB uncorrectable error) doesn't necessarily mean it is a DRAM error.
Remove unused macros while at it.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

The fact whether we are chipkill capable or not does not have any
bearing when computing the channel index on a ganged DCT configuration
so remove that. Also, simplify debug statements. Finally, remove old
error injection leftovers, while at it.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Remove family names from macro names, drop single bit defines and
comment their meaning instead.

No functional change.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Shorten macro names, remove family name from macros, fix macro
arguments, shorten debug strings.

No functionality change.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

* Restrict DCT ganged mode check since only Fam10h supports it
* Adjust DRAM type detection for BD since it only supports DDR3
* Remove second and thus unneeded DCLR read in k8_early_channel_count() - we do
  that in read_mc_regs()
* Cleanup comments and remove family names from register macros
* Remove unused defines

There should be no functional change resulting from this patch.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Do not read DBAM regs twice and simplify code around them.

There should be no functional change resulting from this patch.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Replace hard to read hex constants with a continuous masks macro.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

This function maps the system address to the normalized DCT address.
Document what the code does for more clarity and wrap insane bitmasks in
a more understandable macro which generates them. Also, reduce number of
arguments passed to the function. Finally, rename this function to what
it actually does.

No functional change.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>