DT unit addresses should be lower case hex. Fix all the
binding examples.

Converted with the following command from Krzysztof Kozlowski:

sed -e 's/@\([a-fA-F0-9_-]*\) {/@\L\1 {/' -i $(find Documentation/devicetree/bindings -name '*.txt')
Signed-off-by: NRob Herring <robh@kernel.org>

Improve the binding example by removing all the leading 0x to fix the
following dtc warnings:

Warning (unit_address_format): Node /XXX unit name should not have leading "0x"

Converted using the following command:

find Documentation/devicetree/bindings -name "*.txt" -exec sed -i -e 's/([^ ])\@0x([0-9a-f])/$1\@$2/g' {} +

This is a follow up to commit 48c926cdSigned-off-by: NMathieu Malaterre <malat@debian.org>
Signed-off-by: NRob Herring <robh@kernel.org>

Improve the binding example by removing all the leading zeros to fix the
following dtc warnings:

Warning (unit_address_format): Node /XXX unit name should not have leading 0s

Converted using the following command:

perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find ./Documentation/devicetree/bindings "*.txt"`

Some unnecessary changes were manually fixed.
Signed-off-by: NMarco Franchi <marco.franchi@nxp.com>
Signed-off-by: NRob Herring <robh@kernel.org>

Add all RPM controlled clocks on msm8996 platform

[srini: Fixed various issues with offsets and made names specific to msm8996]
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

These compatible strings need to be added to extend support
for the RPM CC to cover MSM8660/APQ8060. We also need to add
enumberators to the include file for a few clocks that were
missing.

Cc: devicetree@vger.kernel.org
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The concept of "active" clocks is just explained in a bried comment in the
device driver, let's explain it a bit more in the device tree bindings
so everyone understands this.

Cc: devicetree@vger.kernel.org
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The RZ family of Renesas SoCs has several different subfamilies (RZ/A,
RZ/G, RZ/N, and RZ/T).  Clarify that the renesas,rz-cpg-clocks DT
bindings and clk-rz driver apply to RZ/A1 only.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Acked-by: NRob Herring <robh@kernel.org>

Some registers for the Exynos 4412 ISP (Camera subsystem) clocks are
located in the ISP power domain. Because those registers are also
located in a different memory region than the main clock controller,
support for them can be provided by a separate clock controller.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Acked-by: NKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Add a Device Tree binding document for the Broadcom Hurricane 2 SoC
which is an iProc based system.
Acked-by: NJon Mason <jon.mason@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

The clock-cell size is 1 on stm32h7 plaform.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Fixes: 3e4d618b ("clk: stm32h7: Add stm32h743 clock driver")
Signed-off-by: NRob Herring <robh@kernel.org>

Add R-Car V3M (R8A77970) Clock Pulse Generator / Module Standby and
Software Reset support, using the CPG/MSSR driver core and the common
R-Car Gen3 code.

Based on the original (and large) patch by Daisuke Matsushita
<daisuke.matsushita.ns@hitachi.com>.
Signed-off-by: NVladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds support for runtime PM to Exynos Audio SubSystem driver to
enable full support for audio power domain on Exynos5 SoCs. The main change
is moving register saving and restoring code from system sleep PM ops to
runtime PM ops and implementing system sleep PM ops with generic
pm_runtime_force_suspend/resume helpers. Runtime PM of the Exynos AudSS
device is managed from clock core depending on the preparation status
of the provided clocks.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: NUlf Hansson <ulf.hansson@linaro.org>
Reviewed-by: NKrzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1503302703-13801-6-git-send-email-m.szyprowski@samsung.com

Add runtime pm support for all clock controller units (CMU), which belong
to power domains and require special handling during on/off operations.
Typically special values has to be written to MUX registers to change
internal clocks parents to OSC clock before turning power off. During such
operation all clocks, which enter CMU has to be enabled to let MUX to
stabilize. Also for each CMU there is one special parent clock, which has
to be enabled all the time when any access to CMU registers is being done.

This patch solves most of the mysterious external abort and freeze issues
caused by a lack of proper parent CMU clock enabled or incorrect turn off
procedure.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: NUlf Hansson <ulf.hansson@linaro.org>
Reviewed-by: NChanwoo Choi <cw00.choi@samsung.com>
Tested-by: NChanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: NKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1503302703-13801-4-git-send-email-m.szyprowski@samsung.com

Pretty much any node can have a status property, so it doesn't need to
be in examples.

Converted with the following command and removed examples with SoC and
board specific splits:

git grep -l -E 'status.*=.*' Documentation/devicetree/ | xargs sed -i -E '/\sstatus.*=.*"(disabled|ok|okay)/d'
Acked-by: NMark Rutland <mark.rutland@arm.com>
Signed-off-by: NRob Herring <robh@kernel.org>

This new clock driver set allows to have a fractional divided clock that
would generate a precise clock particularly suitable for audio
applications.

The main audio pll clock has two children clocks: one that is connected
to the PMC, the other that can directly drive a pad. As these two routes
have different enable bits and different dividers and divider formulas,
they are handled by two different drivers.

This adds the audio plls (frac, pad and pmc) to the compatible list of
at91 clocks in DT binding.
Signed-off-by: NQuentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: NNicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch enables clocks for STM32H743 boards.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>

for MFD changes:
Acked-by: NLee Jones <lee.jones@linaro.org>

for DT-Bindings
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add basic clock data for Socionext's new SoC PXs3.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

HSDK board manages its clocks using various PLLs. These PLL have same
dividers and corresponding control registers mapped to different addresses.
So we add one common driver for such PLLs.

Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and
ODIV. Output clock value is managed using these dividers.

We add pre-defined tables with supported rate values and appropriate
configurations of IDIV, FBDIV and ODIV for each value.

As of today we add support for PLLs that generate clock for the
HSDK arc cpus, system, ddr, AXI tunnel and hdmi.

By this patch we add support for several plls (arc cpus pll and others),
so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll
and regular probing for others plls.
Signed-off-by: NEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: NVineet Gupta <vgupta@synopsys.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Allwinner A10 is now driven by sunxi-ng CCU driver.

Add devicetree binding for it.
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NPriit Laes <plaes@plaes.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Allwinner A20 is now driven by sunxi-ng CCU driver.

Add devicetree binding for it.
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NPriit Laes <plaes@plaes.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Allwinner R40 has a clock controlling unit like the ones on other
Allwinner SoCs after sun6i, and can also use a CCU-based driver.

Add a compatible string for it.
Signed-off-by: NIcenowy Zheng <icenowy@aosc.io>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NChen-Yu Tsai <wens@csie.org>

R-Car USB 2.0 controller can change the clock source from an oscillator
to an external clock via a register. So, this patch adds support
the clock source selector as a clock driver.
Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Add R-Car D3 (R8A77995) Clock Pulse Generator / Module Standby and
Software Reset support, using the CPG/MSSR driver core and the common
R-Car Gen3 CPG code.

Based on the R-Car Series, 3rd Generation Hardware User's Manual, Rev.
0.55, Jun. 30, 2017.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>
Acked-by: NRob Herring <robh@kernel.org>

The bindings were not updated when the sun5i CCU driver was added in
commit 5e737617 ("clk: sunxi-ng: Add sun5i CCU driver").
Signed-off-by: NJonathan Liu <net147@gmail.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NChen-Yu Tsai <wens@csie.org>

This add bindings documentation for rk3126 SoCs.
Signed-off-by: NElaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

On the first revision of the bindings, only the gates + resets were known
in the AO Clock HW, but more registers used to configures AO clock are known
to be spread among the AO register space.
This patch adds a parent node for the entire system control zone for the AO
domain then moves the clock controller as a subnode of the system control
node.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

This SoC is too old.  It is difficult to maintain any longer.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The Amlogic Meson8/Meson8b/Meson8m2 clock controller provides some reset
lines. These are used for example to boot the secondary CPU cores.

This patch describes the reset controller which is embedded into the
clock controller on these SoCs.
A header file is provided which provides preprocessor macros for each
reset line (to make the .dts files easier to read).
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

The old place is Documentation/devicetree/bindings/clock/ that would
let people hard to find how to use MediaTek cpufreq driver, so moving
it to the appropriate place as other cpufreq drivers done would be
better.
Signed-off-by: NSean Wang <sean.wang@mediatek.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>

IDT VersaClock 5 5P49V5925 has 5 clock outputs, 4 fractional dividers.
Input clock source can be taken only from external reference clock.
Signed-off-by: NVladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

IDT VersaClock 6 5P49V6901 has 4 clock outputs, 4 fractional dividers.
Input clock source can be taken from either external crystal or from
external reference clock.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alexey Firago <alexey_firago@mentor.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: linux-renesas-soc@vger.kernel.org
Cc: devicetree@vger.kernel.org
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

AXS10X boards manages it's clocks using various PLLs. These PLL has same
dividers and corresponding control registers mapped to different addresses.
So we add one common driver for such PLLs.

Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and
ODIV. Output clock value is managed using these dividers.

We add pre-defined tables with supported rate values and appropriate
configurations of IDIV, FBDIV and ODIV for each value.

As of today we add support for PLLs that generate clock for the
following devices:
 * ARC core on AXC CPU tiles.
 * ARC PGU on ARC SDP Mainboard.
and more to come later.

By this patch we add support for two plls (arc core pll and pgu pll),
so we had to use two different init types: CLK_OF_DECLARE for arc core pll and
regular probing for pgu pll.
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NJose Abreu <joabreu@synopsys.com>
Signed-off-by: NEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: NVlad Zakharov <vzakhar@synopsys.com>
Signed-off-by: NJose Abreu <joabreu@synopsys.com>
[sboyd@codeaurora.org: Silence dubious !x & y sparse warning,
make of_axs10x_pll_clk_setup() unregister clk on failure]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The clock consumer usage description was erroneously referring to
couple of dt-binding headers that are no longer valid. The definition
and/or usage of these headers is incorrect and the only file present
at the moment, dt-bindings/soc/k2g.h is also being cleaned up. The
examples in this binding were updated properly, but the update to
description was missed out. So, fix this.

Fixes: 8f306cfe ("Documentation: dt: Add TI SCI clock driver")
Signed-off-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NRob Herring <robh@kernel.org>

checkpatch.pl doesn't know how to expand "silabs,si5351{a,a-msop,b,c}"
and so generates warnings about si5351-compatible devices appearing to
be un-documented. Resolve this by documenting the compatible options
supported by the clk-si5351 driver individually.
Signed-off-by: NBrandon Streiff <brandon.streiff@ni.com>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NRob Herring <robh@kernel.org>

Add device tree binding documentation for the clocks provided by the
MIPS Boston development board from Imagination Technologies, and a
header file describing the available clocks for use by device trees &
driver.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>
Cc: Frank Rowand <frowand.list@gmail.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16482/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Update iproc clock dt-binding documentation with
Stingray pll and clock details.
Signed-off-by: NSandeep Tripathy <sandeep.tripathy@broadcom.com>
Reviewed-by: NRay Jui <ray.jui@broadcom.com>
Reviewed-by: NScott Branden <scott.branden@broadcom.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add acpu clock, including sft clock controlling hi6220 coresight module
Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: NLi Pengcheng <lipengcheng8@huawei.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add the compatible strings and the include file for ipq8074 gcc
clock controller.

Acked-by: Rob Herring <robh@kernel.org> (bindings)
Signed-off-by: NVaradarajan Narayanan <varada@codeaurora.org>
Signed-off-by: NAbhishek Sahu <absahu@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Texas Instruments omap variant SoCs starting with omap4 have a clkctrl
clock controller instance for each interconnect target module. The clkctrl
controls functional and interface clocks for the module.

The clkctrl clocks are currently handled by arch/arm/mach-omap2 hwmod code.
With this binding and a related clock device driver we can start moving the
clkctrl clock handling to live in drivers/clk/ti.

Note that this binding allows keeping the clockdomain related parts out of
drivers/clock. The CLKCTCTRL and DYNAMICDEP registers can be handled by
a separate driver in drivers/soc/ti and genpd. If the clockdomain driver
needs to know it's clocks, we can just set the the clkctrl device
instances to be children of the related clockdomain device.

Each clkctrl clock can have multiple optional gate clocks, and multiple
optional mux clocks. To represent this in device tree, it seems that
it is best done using four clock cells #clock-cells = <2> property.

The reasons for using #clock-cells = <2> are:

1. We need to specify the clkctrl offset from the instance base. Otherwise
   we end up with a large number of device tree nodes that need to be
   patched when new clocks are discovered in a clkctrl clock with minor
   hardware revision changes for example

2. On omap5 CM_L3INIT_USB_HOST_HS_CLKCTRL has ten OPTFCLKEN bits. So we
   need to use a separate cell for optional gate clocks to avoid address
   space conflicts

There is probably no need to list input clocks for each clkctrl clock
instance in the binding. If we want to add them, the standard clocks
binding can be used for that.

For hardware reference, see omap4430 TRM "Table 3-1312. L4PER_CM2 Registers
Mapping Summary" for example. It shows one instance of a clkctrl clock
controller with multiple clkctrl registers.

Cc: Paul Walmsley <paul@pwsan.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NTero Kristo <t-kristo@ti.com>

Add a clock implementation, TI SCI clock, that will hook to the common
clock framework, and allow each clock to be controlled via TI SCI
protocol.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>