1. 19 9月, 2016 1 次提交
  2. 29 8月, 2016 1 次提交
  3. 17 8月, 2016 1 次提交
  4. 16 8月, 2016 1 次提交
    • D
      drm: Extract drm_framebuffer.[hc] · 7520a277
      Daniel Vetter 提交于
      Also start with drm_modeset.h with the core bits, since we need
      to untangle this mess somehow. That allows us to move the drm_modes.h
      include to the right spot, except for the temporary connector status
      enum. That will get fixed as soon as drm_connector.h exists.
      
      v2: Rebase.
      
      v3: Move drm_crtc_force_disable_all back again, that wasn't meant to
      be moved (Sean).
      
      v4: Rebase.
      
      Cc: Sean Paul <seanpaul@chromium.org>
      Reviewed-by: NSean Paul <seanpaul@chromium.org>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      7520a277
  5. 08 8月, 2016 2 次提交
  6. 04 6月, 2016 1 次提交
  7. 11 12月, 2015 2 次提交
  8. 09 12月, 2015 1 次提交
  9. 01 12月, 2015 1 次提交
    • V
      drm/edid: Make the detailed timing CEA/HDMI mode fixup accept up to 5kHz clock difference · 4c6bcf44
      Ville Syrjälä 提交于
      Rather than using drm_match_cea_mode() to see if the EDID detailed
      timings are supposed to represent one of the CEA/HDMI modes, add a
      special version of that function that takes in an explicit clock
      tolerance value (in kHz). When looking at the detailed timings specify
      the tolerance as 5kHz due to the 10kHz clock resolution limit inherent
      in detailed timings.
      
      drm_match_cea_mode() uses the normal KHZ2PICOS() matching of clocks,
      which only allows smaller errors for lower clocks (eg. for 25200 it
      won't allow any error) and a bigger error for higher clocks (eg. for
      297000 it actually matches 296913-297000). So it doesn't really match
      what we want for the fixup. Using the explicit +-5kHz is much better
      for this use case.
      
      Not sure if we should change the normal mode matching to also use
      something else besides KHZ2PICOS() since it allows a different
      proportion of error depending on the clock. I believe VESA CVT
      allows a maximum deviation of .5%, so using that for normal mode
      matching might be a good idea?
      
      Cc: Adam Jackson <ajax@redhat.com>
      Tested-by: nathan.d.ciobanu@linux.intel.com
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92217
      Fixes: fa3a7340 ("drm/edid: Fix up clock for CEA/HDMI modes specified via detailed timings")
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: NAdam Jackson <ajax@redhat.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      4c6bcf44
  10. 22 5月, 2015 1 次提交
  11. 23 2月, 2015 1 次提交
  12. 08 1月, 2015 1 次提交
  13. 18 12月, 2014 2 次提交
  14. 06 12月, 2014 1 次提交
  15. 01 5月, 2014 1 次提交
  16. 13 3月, 2014 6 次提交